| A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector S Choi, S Yoo, Y Lim, J Choi IEEE Journal of Solid-State Circuits 51 (8), 1878-1889, 2016 | 83 | 2016 |
| An external capacitorless low-dropout regulator with high PSR at all frequencies from 10 kHz to 1 GHz using an adaptive supply-ripple cancellation technique Y Lim, J Lee, S Park, Y Jo, J Choi IEEE Journal of Solid-State Circuits 53 (9), 2675-2685, 2018 | 71 | 2018 |
| 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced … J Kim, H Yoon, Y Lim, Y Lee, Y Cho, T Seong, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2019 | 67 | 2019 |
| A− 31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection … H Yoon, J Kim, S Park, Y Lim, Y Lee, J Bang, K Lim, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 366-368, 2018 | 51 | 2018 |
| A 0.56–2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G–4G Multistandard Cellular Transceivers H Yoon, Y Lee, Y Lim, GY Tak, HT Kim, YC Ho, J Choi IEEE Journal of Solid-State Circuits 51 (3), 614-625, 2016 | 39 | 2016 |
| An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators J Kim, Y Lim, H Yoon, Y Lee, H Park, Y Cho, T Seong, J Choi IEEE Journal of Solid-State Circuits 54 (12), 3466-3477, 2019 | 33 | 2019 |
| An external capacitor-less ultralow-dropout regulator using a loop-gain stabilizing technique for high power-supply rejection over a wide range of load current Y Lim, J Lee, Y Lee, SS Song, HT Kim, O Lee, J Choi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (11 …, 2017 | 29 | 2017 |
| An extemal-capacitor-less low-dropout regulator with less than− 36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the … Y Lim, J Lee, S Park, J Choi 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 28 | 2017 |
| 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique J Kim, Y Jo, Y Lim, T Seong, H Park, S Yoo, Y Lee, S Choi, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 448-450, 2021 | 24 | 2021 |
| A 65-nm CMOSMIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations K Lim, S Lee, Y Lee, B Moon, H Shin, K Kang, S Kim, J Lee, H Lee, ... IEEE Journal of Solid-State Circuits 53 (7), 1960-1976, 2018 | 22 | 2018 |
| 17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power … Y Lim, J Kim, Y Jo, J Bang, S Yoo, H Park, H Yoon, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 280-282, 2020 | 21 | 2020 |
| 30.9 A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope … S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 490-492, 2019 | 20 | 2019 |
| A low-jitter and low-reference-spur ring-VCO-based injection-locked clock multiplier using a triple-point background calibrator S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi IEEE Journal of Solid-State Circuits 56 (1), 298-309, 2020 | 17 | 2020 |
| An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114 S Choi, S Yoo, Y Lee, Y Jo, J Lee, Y Lim, J Choi IEEE Journal of Solid-State Circuits 54 (4), 927-936, 2018 | 15 | 2018 |
| A fast-transient and high-accuracy, adaptive-sampling digital LDO using a single-VCO-based edge-racing time quantizer J Lee, J Bang, Y Lim, S Yoo, Y Lee, T Seong, J Choi IEEE solid-state circuits letters 2 (12), 305-308, 2019 | 11 | 2019 |
| A 320µV-output ripple and 90ns-settling time at 0.5 V supply digital-analog-hybrid LDO using multi-level gate-voltage generator and fast-decision PD detector Y Lim, J Lee, Y Lee, S Yoo, J Choi ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 11 | 2018 |
| A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer J Lee, J Bang, Y Lim, J Choi 2019 Symposium on VLSI Circuits, C130-C131, 2019 | 9 | 2019 |
| A wide-lock-in-range and low-jitter 12–14.5 GHz SSPLL using a low-power frequency-disturbance-detecting and correcting loop Y Lim, J Kim, Y Jo, J Bang, J Choi IEEE Journal of Solid-State Circuits 57 (2), 480-491, 2021 | 7 | 2021 |
| A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier Y Jo, J Kim, Y Shin, H Park, C Hwang, Y Lim, J Choi IEEE Journal of Solid-State Circuits, 2023 | 5 | 2023 |
| 153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier S Choi, S Yoo, Y Lee, Y Jo, J Lee, Y Lim, J Choi 2018 IEEE Symposium on VLSI Circuits, 185-186, 2018 | 4 | 2018 |
