| A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a $42.5\;\upmu\text {W} $100 kb/s Super-Regenerative Transceiver for Body Channel Communication H Cho, H Kim, M Kim, J Jang, Y Lee, KJ Lee, J Bae, HJ Yoo IEEE journal of solid-state circuits 51 (1), 310-317, 2015 | 125 | 2015 |
| A 82-nW chaotic map true random number generator based on a sub-ranging SAR ADC M Kim, U Ha, KJ Lee, Y Lee, HJ Yoo IEEE Journal of Solid-State Circuits 52 (7), 1953-1965, 2017 | 106 | 2017 |
| Tunnelling-based ternary metal–oxide–semiconductor technology JW Jeong, YE Choi, WS Kim, JH Park, S Kim, S Shin, K Lee, J Chang, ... Nature Electronics 2 (7), 307-312, 2019 | 97 | 2019 |
| A 1.4-m -Sensitivity 94-dB Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub-SoC for 3-D Lung Ventilation Monitoring System M Kim, J Jang, H Kim, J Lee, J Lee, J Lee, KR Lee, K Kim, Y Lee, KJ Lee, ... IEEE Journal of Solid-State Circuits 52 (11), 2829-2842, 2017 | 73 | 2017 |
| A 9.02 mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices S Choi, J Lee, K Lee, HJ Yoo 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 220-222, 2018 | 53 | 2018 |
| A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition J Park, I Hong, G Kim, Y Kim, K Lee, S Park, K Bong, HJ Yoo 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 51 | 2013 |
| A 1.22 TOPS and 1.52 mW/MHz augmented reality multicore processor with neural network NoC for HMD applications G Kim, K Lee, Y Kim, S Park, I Hong, K Bong, HJ Yoo IEEE Journal of Solid-State Circuits 50 (1), 113-124, 2014 | 49 | 2014 |
| A 502-GOPS and 0.984-mW dual-mode intelligent ADAS SoC with real-time semiglobal matching and intention prediction for smart automotive black box system KJ Lee, K Bong, C Kim, J Jang, KR Lee, J Lee, G Kim, HJ Yoo IEEE Journal of Solid-State Circuits 52 (1), 139-150, 2016 | 37 | 2016 |
| 17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator … T Seong, Y Lee, C Hwang, J Lee, H Park, KJ Lee, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2020 | 29 | 2020 |
| An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications C Kim, K Bong, I Hong, K Lee, S Choi, HJ Yoo ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 255-258, 2017 | 27 | 2017 |
| A low-power, mixed-mode neural network classifier for robust scene classification K Lee, J Park, HJ Yoo Journal of Semiconductor Technology and Science 19 (1), 129-136, 2019 | 26 | 2019 |
| 14.2 a 502gops and 0.984 mw dual-mode adas soc with rnn-fis engine for intention prediction in automotive black-box system KJ Lee, K Bong, C Kim, J Jang, H Kim, J Lee, KR Lee, G Kim, HJ Yoo 2016 IEEE International Solid-State Circuits Conference (ISSCC), 256-257, 2016 | 26 | 2016 |
| A 2.71 nJ/pixel gaze-activated object recognition system for low-power mobile smart glasses I Hong, K Bong, D Shin, S Park, KJ Lee, Y Kim, HJ Yoo IEEE Journal of Solid-State Circuits 51 (1), 45-55, 2015 | 26 | 2015 |
| A vocabulary forest object matching processor with 2.07 M-vector/s throughput and 13.3 nJ/vector per-vector energy for full-HD 60 fps video object recognition KJ Lee, G Kim, J Park, HJ Yoo IEEE Journal of Solid-State Circuits 50 (4), 1059-1069, 2015 | 20 | 2015 |
| 18.1 A 2.71 nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications I Hong, K Bong, D Shin, S Park, K Lee, Y Kim, HJ Yoo 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 19* | 2015 |
| The development of silicon for AI: Different design approaches KJ Lee, J Lee, S Choi, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4719-4732, 2020 | 14 | 2020 |
| A multi-modal and tunable Radial-Basis-Funtion circuit with supply and temperature compensation K Lee, J Park, G Kim, I Hong, HJ Yoo 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1608-1611, 2013 | 13 | 2013 |
| Architecture of neural processing unit for deep neural networks KJ Lee Advances in Computers 122, 217-245, 2021 | 6 | 2021 |
| A 31.2 pJ/disparity· pixel stereo matching processor with stereo SRAM for mobile UI application J Lee, D Shin, K Lee, HJ Yoo 2017 Symposium on VLSI Circuits, C158-C159, 2017 | 6 | 2017 |
| A cmos image sensor-based stereo matching accelerator with focal-plane sparse rectification and analog census transform C Kim, K Bong, S Choi, KJ Lee, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 63 (12), 2180-2188, 2016 | 6 | 2016 |
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