| A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector S Choi, S Yoo, Y Lim, J Choi IEEE Journal of Solid-State Circuits 51 (8), 1878-1889, 2016 | 83 | 2016 |
| A low-integrated-phase-noise 27–30-GHz injection-locked frequency multiplier with an ultra-low-power frequency-tracking loop for mm-wave-band 5G transceivers S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi IEEE Journal of Solid-State Circuits 53 (2), 375-388, 2017 | 61 | 2017 |
| 10.7 A 185fsrms-integrated-jitter and− 245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay … S Choi, S Yoo, J Choi 2016 IEEE International Solid-State Circuits Conference (ISSCC), 194-195, 2016 | 49 | 2016 |
| A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique Y Lee, T Seong, S Yoo, J Choi IEEE Journal of Solid-State Circuits 53 (4), 1192-1202, 2017 | 42 | 2017 |
| A 320-fs RMS jitter and–75-dBc reference-spur ring-DCO-based digital PLL using an optimal-threshold TDC T Seong, Y Lee, S Yoo, J Choi IEEE Journal of Solid-State Circuits 54 (9), 2501-2512, 2019 | 36 | 2019 |
| A 2–8 GHz Wideband Dually Frequency-Tuned Ring-VCO With a Scalable S Yoo, JJ Kim, J Choi IEEE microwave and wireless components letters 23 (11), 602-604, 2013 | 27 | 2013 |
| 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique J Kim, Y Jo, Y Lim, T Seong, H Park, S Yoo, Y Lee, S Choi, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 448-450, 2021 | 24 | 2021 |
| A− 242dB FOM and− 75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC T Seong, Y Lee, S Yoo, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2018 | 22 | 2018 |
| 17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power … Y Lim, J Kim, Y Jo, J Bang, S Yoo, H Park, H Yoon, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 280-282, 2020 | 21 | 2020 |
| 30.9 A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope … S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 490-492, 2019 | 20 | 2019 |
| A− 242-dB FOM and− 71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique T Seong, Y Lee, S Yoo, J Choi 2017 Symposium on VLSI Circuits, C186-C187, 2017 | 20 | 2017 |
| A low-jitter and low-reference-spur ring-VCO-based injection-locked clock multiplier using a triple-point background calibrator S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi IEEE Journal of Solid-State Circuits 56 (1), 298-309, 2020 | 17 | 2020 |
| An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114 S Choi, S Yoo, Y Lee, Y Jo, J Lee, Y Lim, J Choi IEEE Journal of Solid-State Circuits 54 (4), 927-936, 2018 | 15 | 2018 |
| 23.4 An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS S Yoo, S Park, S Choi, Y Cho, H Yoon, C Hwang, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 330-332, 2021 | 13 | 2021 |
| A fast-transient and high-accuracy, adaptive-sampling digital LDO using a single-VCO-based edge-racing time quantizer J Lee, J Bang, Y Lim, S Yoo, Y Lee, T Seong, J Choi IEEE solid-state circuits letters 2 (12), 305-308, 2019 | 11 | 2019 |
| A 320µV-output ripple and 90ns-settling time at 0.5 V supply digital-analog-hybrid LDO using multi-level gate-voltage generator and fast-decision PD detector Y Lim, J Lee, Y Lee, S Yoo, J Choi ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 11 | 2018 |
| An ultra-low jitter, low-power, 102-GHz PLL using a power-gating injection-locked frequency multiplier-based phase detector S Park, S Choi, S Yoo, Y Cho, J Choi IEEE Journal of Solid-State Circuits 57 (9), 2829-2840, 2021 | 9 | 2021 |
| 19.2 A PVT-robust− 39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase … S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi 2017 IEEE International Solid-State Circuits Conference (ISSCC), 324-325, 2017 | 9 | 2017 |
| A 0.1–1.5-GHz wide harmonic-locking-free delay-locked loop using an exponential DAC S Park, J Kim, C Hwang, H Park, S Yoo, T Seong, J Choi IEEE Microwave and Wireless Components Letters 29 (8), 548-550, 2019 | 7 | 2019 |
| A sub-100 fs-jitter 8.16-GHz ring-oscillator-based power-gating injection-locked clock multiplier with the multiplication factor of 68 S Park, S Yoo, Y Shin, J Lee, J Choi IEEE Journal of Solid-State Circuits 58 (1), 78-89, 2022 | 6 | 2022 |
