| High-resolution electrohydrodynamic inkjet printing of stretchable metal oxide semiconductor transistors with high performance SY Kim, K Kim, YH Hwang, J Park, J Jang, Y Nam, Y Kang, M Kim, ... Nanoscale 8 (39), 17113-17121, 2016 | 120 | 2016 |
| A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector S Choi, S Yoo, Y Lim, J Choi IEEE Journal of Solid-State Circuits 51 (8), 1878-1889, 2016 | 83 | 2016 |
| An external capacitorless low-dropout regulator with high PSR at all frequencies from 10 kHz to 1 GHz using an adaptive supply-ripple cancellation technique Y Lim, J Lee, S Park, Y Jo, J Choi IEEE Journal of Solid-State Circuits 53 (9), 2675-2685, 2018 | 71 | 2018 |
| 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced … J Kim, H Yoon, Y Lim, Y Lee, Y Cho, T Seong, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2019 | 67 | 2019 |
| A low-integrated-phase-noise 27–30-GHz injection-locked frequency multiplier with an ultra-low-power frequency-tracking loop for mm-wave-band 5G transceivers S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi IEEE Journal of Solid-State Circuits 53 (2), 375-388, 2017 | 61 | 2017 |
| A ring VCO with wide and linear tuning characteristics for a cognitive radio system J Choi, K Lim, J Laskar 2008 IEEE Radio Frequency Integrated Circuits Symposium, 395-398, 2008 | 56 | 2008 |
| High multiplication factor capacitor multiplier for an on-chip PLL loop filter J Choi, J Park, W Kim, K Lim, J Laskar Electronics Letters 45 (5), 239-240, 2009 | 53 | 2009 |
| A− 31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection … H Yoon, J Kim, S Park, Y Lim, Y Lee, J Bang, K Lim, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 366-368, 2018 | 51 | 2018 |
| 10.7 A 185fsrms-integrated-jitter and− 245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay … S Choi, S Yoo, J Choi 2016 IEEE International Solid-State Circuits Conference (ISSCC), 194-195, 2016 | 49 | 2016 |
| A low-jitter and fractional-resolution injection-locked clock multiplier using a DLL-based real-time PVT calibrator with replica-delay cells M Kim, S Choi, T Seong, J Choi IEEE Journal of Solid-State Circuits 51 (2), 401-411, 2015 | 49 | 2015 |
| A Wideband Dual-Mode -VCO With a Switchable Gate-Biased Active Core H Yoon, Y Lee, JJ Kim, J Choi IEEE Transactions on Circuits and Systems II: Express Briefs 61 (5), 289-293, 2014 | 45 | 2014 |
| A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique Y Lee, T Seong, S Yoo, J Choi IEEE Journal of Solid-State Circuits 53 (4), 1192-1202, 2017 | 42 | 2017 |
| A 0.56–2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G–4G Multistandard Cellular Transceivers H Yoon, Y Lee, Y Lim, GY Tak, HT Kim, YC Ho, J Choi IEEE Journal of Solid-State Circuits 51 (3), 614-625, 2016 | 39 | 2016 |
| A spur suppression technique using an edge-interpolator for a charge-pump PLL J Choi, W Kim, K Lim IEEE transactions on very large scale integration (VLSI) systems 20 (5), 969-973, 2011 | 39 | 2011 |
| A 320-fs RMS jitter and–75-dBc reference-spur ring-DCO-based digital PLL using an optimal-threshold TDC T Seong, Y Lee, S Yoo, J Choi IEEE Journal of Solid-State Circuits 54 (9), 2501-2512, 2019 | 35 | 2019 |
| A 122-mW low-power multiresolution spectrum-sensing IC with self-deactivated partial swing techniques T Song, J Park, SM Lee, J Choi, K Kim, CH Lee, K Lim, J Laskar IEEE Transactions on Circuits and Systems II: Express Briefs 57 (3), 188-192, 2010 | 35 | 2010 |
| An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators J Kim, Y Lim, H Yoon, Y Lee, H Park, Y Cho, T Seong, J Choi IEEE Journal of Solid-State Circuits 54 (12), 3466-3477, 2019 | 33 | 2019 |
| 17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator … T Seong, Y Lee, C Hwang, J Lee, H Park, KJ Lee, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2020 | 29 | 2020 |
| An external capacitor-less ultralow-dropout regulator using a loop-gain stabilizing technique for high power-supply rejection over a wide range of load current Y Lim, J Lee, Y Lee, SS Song, HT Kim, O Lee, J Choi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (11 …, 2017 | 29 | 2017 |
| An extemal-capacitor-less low-dropout regulator with less than− 36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the … Y Lim, J Lee, S Park, J Choi 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 28 | 2017 |
Yongsun Lee (이용선)Memory division, Samsung Electronicssamsung.com의 이메일 확인됨
