| Cvc4 C Barrett, CL Conway, M Deters, L Hadarean, D Jovanović, T King, ... International Conference on Computer Aided Verification, 171-177, 2011 | 1195 | 2011 |
| A DPLL (T) theory solver for a theory of strings and regular expressions T Liang, A Reynolds, C Tinelli, C Barrett, M Deters International Conference on Computer Aided Verification, 646-662, 2014 | 138 | 2014 |
| Counterexample-guided quantifier instantiation for synthesis in SMT A Reynolds, M Deters, V Kuncak, C Tinelli, C Barrett International Conference on Computer Aided Verification, 198-216, 2015 | 137* | 2015 |
| Induction for SMT solvers A Reynolds, V Kuncak International Workshop on Verification, Model Checking, and Abstract …, 2015 | 87 | 2015 |
| Finding conflicting instances of quantified formulas in SMT A Reynolds, C Tinelli, L De Moura 2014 Formal Methods in Computer-Aided Design (FMCAD), 195-202, 2014 | 75 | 2014 |
| Quantifier instantiation techniques for finite model finding in SMT A Reynolds, C Tinelli, A Goel, S Krstić, M Deters, C Barrett International Conference on Automated Deduction, 377-391, 2013 | 72 | 2013 |
| Finite model finding in SMT A Reynolds, C Tinelli, A Goel, S Krstić International Conference on Computer Aided Verification, 640-655, 2013 | 66 | 2013 |
| SMT proof checking using a logical framework A Stump, D Oe, A Reynolds, L Hadarean, C Tinelli Formal Methods in System Design 42 (1), 91-118, 2013 | 64 | 2013 |
| SMTCoq: A plug-in for integrating SMT solvers into Coq B Ekici, A Mebsout, C Tinelli, C Keller, G Katz, A Reynolds, C Barrett International Conference on Computer Aided Verification, 126-133, 2017 | 62 | 2017 |
| A tour of CVC4: how it works, and how to use it M Deters, A Reynolds, T King, C Barrett, C Tinelli 2014 Formal Methods in Computer-Aided Design (FMCAD), 7-7, 2014 | 52 | 2014 |
| An efficient SMT solver for string constraints T Liang, A Reynolds, N Tsiskaridze, C Tinelli, C Barrett, M Deters Formal Methods in System Design 48 (3), 206-234, 2016 | 48 | 2016 |
| cvc4sy: Smart and Fast Term Enumeration for Syntax-Guided Synthesis A Reynolds, H Barbosa, A Nötzli, C Barrett, C Tinelli International Conference on Computer Aided Verification, 74-83, 2019 | 44 | 2019 |
| A decision procedure for (co) datatypes in SMT solvers A Reynolds, JC Blanchette International Conference on Automated Deduction, 197-213, 2015 | 40 | 2015 |
| Revisiting enumerative instantiation A Reynolds, H Barbosa, P Fontaine International Conference on Tools and Algorithms for the Construction and …, 2018 | 39 | 2018 |
| Congruence closure with free variables H Barbosa, P Fontaine, A Reynolds International Conference on Tools and Algorithms for the Construction and …, 2017 | 35 | 2017 |
| A decision procedure for separation logic in SMT A Reynolds, R Iosif, C Serban, T King International Symposium on Automated Technology for Verification and …, 2016 | 35 | 2016 |
| Extending SMT solvers to higher-order logic H Barbosa, A Reynolds, D El Ouraoui, C Tinelli, C Barrett International Conference on Automated Deduction, 35-54, 2019 | 34* | 2019 |
| Solving quantified linear arithmetic by counterexample-guided instantiation A Reynolds, T King, V Kuncak Formal Methods in System Design 51 (3), 500-532, 2017 | 34* | 2017 |
| Scaling up DPLL (T) string solvers using context-dependent simplification A Reynolds, M Woo, C Barrett, D Brumley, T Liang, C Tinelli International Conference on Computer Aided Verification, 453-474, 2017 | 31 | 2017 |
| Solving quantified bit-vectors using invertibility conditions A Niemetz, M Preiner, A Reynolds, C Barrett, C Tinelli International Conference on Computer Aided Verification, 236-255, 2018 | 29 | 2018 |
Cesare TinelliProfessor of Computer Science, The University of Iowauiowa.edu의 이메일 확인됨
