| Double planar gated SOI MOSFET structure JW Adkisson, JA Bracchitta, JJ Ellis-Monaghan, JB Lasky, E Leobandung, ... US Patent 6,483,156, 2002 | 202 | 2002 |
| Embedded DRAM on silicon-on-insulator substrate JW Adkisson, R Divakaruni, JP Gambino, JA Mandelman US Patent 6,350,653, 2002 | 175* | 2002 |
| Damascene copper wiring image sensor JW Adkisson, JP Gambino, MD Jaffe, RK Leidy, AK Stamper US Patent 7,193,289, 2007 | 172 | 2007 |
| CMOS imager array with recessed dielectric JW Adkisson, JP Gambino, ZX He, MD Jaffe, RK Leidy, SE Luce, ... US Patent 7,781,781, 2010 | 162 | 2010 |
| Semiconductor device of an embedded DRAM on SOI substrate JW Adkisson, R Divakaruni, JP Gambino, JA Mandelman US Patent 6,590,259, 2003 | 159 | 2003 |
| Double planar gated SOI MOSFET structure JW Adkisson, JA Bracchitta, JJ Ellis-Monaghan, JB Lasky, E Leobandung, ... US Patent 6,483,156, 2002 | 144 | 2002 |
| Double gate trench transistor JW Adkisson, PD Agnello, AW Ballantine, R Divakaruni, EC Jones, ... US Patent 6,472,258, 2002 | 119 | 2002 |
| Method for making multiple threshold voltage FET using multiple work-function gate materials JW Adkisson, AW Ballantine, R Divakaruni, JB Johnson, EC Jones, ... US Patent 6,797,553, 2004 | 118 | 2004 |
| Stacked imager package JW Adkisson, JP Gambino, MD Jaffe, RK Leidy, SE Luce, RJ Rassel, ... US Patent 7,361,989, 2008 | 117 | 2008 |
| A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications JJ Pekarik, J Adkisson, P Gray, Q Liu, R Camillo-Castillo, M Khater, V Jain, ... 2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 92-95, 2014 | 104 | 2014 |
| Stacked imager package JW Adkisson, JP Gambino, MD Jaffe, RK Leidy, SE Luce, RJ Rassel, ... US Patent 7,361,989, 2008 | 103 | 2008 |
| Stacked imager package JW Adkisson, JP Gambino, MD Jaffe, RK Leidy, SE Luce, RJ Rassel, ... US Patent 7,361,989, 2008 | 103 | 2008 |
| Method of fabricating semiconductor side wall fin JW Adkisson, PD Agnello, AW Ballantine, R Divakaruni, EC Jones, ... US Patent 7,265,417, 2007 | 79 | 2007 |
| Method of fabricating semiconductor side wall fin JW Adkisson, PD Agnello, AW Ballantine, R Divakaruni, EC Jones, ... US Patent 7,265,417, 2007 | 79 | 2007 |
| Damascene copper wiring optical image sensor JW Adkisson, JP Gambino, MD Jaffe, RK Leidy, AK Stamper US Patent 7,655,495, 2010 | 77 | 2010 |
| CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom JW Adkisson, JP Gambino, MD Jaffe, RK Leidy, RJ Rassel, AK Stamper US Patent 7,772,028, 2010 | 76 | 2010 |
| CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom JW Adkisson, JP Gambino, MD Jaffe, RK Leidy, RJ Rassel, AK Stamper US Patent 7,772,028, 2010 | 76 | 2010 |
| Pixel sensor structure including light pipe and method for fabrication thereof K Ackerson, J Adkisson, J Ellis-Monaghan, J Gambino, T Hoague, M Jaffe, ... US Patent App. 11/276,160, 2007 | 74 | 2007 |
| Process for defining a pattern using an anti-reflective coating and structure therefor JW Adkisson, M Caterer, JT Marsh, H Ng, JM Oberschmidt, JH Rankin US Patent 6,030,541, 2000 | 74 | 2000 |
| Method of adding fabrication monitors to integrated circuit chips JW Adkisson, G Bazan, JM Cohn, MS Grady, TG Sopchak, DP Vallett US Patent 7,240,322, 2007 | 66 | 2007 |
