| Efficient computation reduction in Bayesian neural networks through feature decomposition and memorization X Jia, J Yang, R Liu, X Wang, SD Cotofana, W Zhao IEEE transactions on neural networks and learning systems 32 (4), 1703-1712, 2020 | 28 | 2020 |
| Secure and low-overhead circuit obfuscation technique with multiplexers X Wang, X Jia, Q Zhou, Y Cai, J Yang, M Gao, G Qu Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 133-136, 2016 | 27 | 2016 |
| A multicommodity flow-based detailed router with efficient acceleration techniques X Jia, Y Cai, Q Zhou, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 23 | 2017 |
| Spintronics based stochastic computing for efficient Bayesian inference system X Jia, J Yang, Z Wang, Y Chen, HH Li, W Zhao 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 580-585, 2018 | 22 | 2018 |
| MCFRoute: A detailed router based on multi-commodity flow method X Jia, Y Cai, Q Zhou, G Chen, Z Li, Z Li 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 397-404, 2014 | 22 | 2014 |
| SPINBIS: Spintronics-based Bayesian inference system with stochastic computing X Jia, J Yang, P Dai, R Liu, Y Chen, W Zhao IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 20 | 2019 |
| Triangle counting accelerations: From algorithm to in-memory computing architecture X Wang, J Yang, Y Zhao, X Jia, R Yin, X Chen, G Qu, W Zhao IEEE Transactions on Computers 71 (10), 2462-2472, 2021 | 14 | 2021 |
| Accelerating graph-connected component computation with emerging processing-in-memory architecture X Chen, X Wang, X Jia, J Yang, G Qu, W Zhao IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 11 | 2022 |
| NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration Y Zhao, J Yang, B Li, X Cheng, X Ye, X Wang, X Jia, Z Wang, Y Zhang, ... Science China Information Sciences 66 (4), 142401, 2023 | 10 | 2023 |
| High on/off ratio spintronic multi‐level memory unit for deep neural network K Zhang, X Jia, K Cao, J Wang, Y Zhang, K Lin, L Chen, X Feng, Z Zheng, ... Advanced Science 9 (13), 2103357, 2022 | 8 | 2022 |
| TCIM: triangle counting acceleration with processing-in-MRAM architecture X Wang, J Yang, Y Zhao, Y Qi, M Liu, X Cheng, X Jia, X Chen, G Qu, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 8 | 2020 |
| An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing Y Pan, X Jia, Z Cheng, P Ouyang, X Wang, J Yang, W Zhao CCF Transactions on High Performance Computing 2, 272-281, 2020 | 7 | 2020 |
| IMGA: Efficient in-memory graph convolution network aggregation with data flow optimizations Y Wei, X Wang, S Zhang, J Yang, X Jia, Z Wang, G Qu, W Zhao IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 6 | 2023 |
| An energy-efficient Bayesian neural network implementation using stochastic computing method X Jia, H Gu, Y Liu, J Yang, X Wang, W Pan, Y Zhang, S Cotofana, W Zhao IEEE Transactions on Neural Networks and Learning Systems, 2023 | 6 | 2023 |
| Msfroute: Multi-stage fpga routing for timing division multiplexing technique Z Zhuang, G Liu, X Huang, X Jia, WH Liu, W Guo Proceedings of the 2020 on Great Lakes Symposium on VLSI, 107-112, 2020 | 6 | 2020 |
| Hardware security in spin-based computing-in-memory: Analysis, exploits, and mitigation techniques X Wang, J Yang, Y Zhao, X Jia, G Qu, W Zhao ACM Journal on Emerging Technologies in Computing Systems (JETC) 16 (4), 1-18, 2020 | 6 | 2020 |
| Mcfroute 2.0: A redundant via insertion enhanced concurrent detailed router X Jia, Y Cai, Q Zhou, B Yu Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 87-92, 2016 | 4 | 2016 |
| Spintronic solutions for stochastic computing X Jia, Y Wang, Z Huang, Y Zhang, J Yang, Y Qu, BF Cockburn, J Han, ... Stochastic Computing: Techniques and Applications, 165-183, 2019 | 2 | 2019 |
| DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-Based Processing-In-Memory C Duan, J Yang, X He, Y Qi, Y Wang, Y Wang, Z He, B Yan, X Wang, X Jia, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 1 | 2023 |
| Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity C Duan, J Yang, Y Wang, Y Wang, Y Qi, X He, B Yan, X Wang, X Jia, ... arXiv preprint arXiv:2404.09497, 2024 | | 2024 |
Jianlei YangBeihang Universitybuaa.edu.cn의 이메일 확인됨
