| Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM N Kim, J Ahn, W Seo, K Choi 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 18 | 2015 |
| Exploration of trade-offs in the design of volatile STT–RAM cache N Kim, K Choi Journal of Systems Architecture 71, 23-31, 2016 | 15 | 2016 |
| Acceleration of DNN backward propagation by selective computation of gradients G Lee, H Park, N Kim, J Yu, S Jo, K Choi Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 14 | 2019 |
| Benzene: An energy-efficient distributed hybrid cache architecture for manycore systems N Kim, J Ahn, K Choi, D Sanchez, D Yoo, S Ryu ACM Transactions on Architecture and Code Optimization (TACO) 15 (1), 1-23, 2018 | 12 | 2018 |
| NVDIMM-C: A byte-addressable non-volatile memory module for compatibility with standard DDR memory interfaces C Lee, W Shin, DJ Kim, Y Yu, SJ Kim, T Ko, D Seo, J Park, K Lee, S Choi, ... 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 10 | 2020 |
| A design guideline for volatile STT-RAM with ECC and scrubbing N Kim, K Choi 2015 International SoC Design Conference (ISOCC), 29-30, 2015 | 9 | 2015 |
| Sgcn: Exploiting compressed-sparse features in deep graph convolutional network accelerators M Yoo, J Song, J Lee, N Kim, Y Kim, J Lee 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 7 | 2023 |
| Computing apparatus and method for cache management N Kim, AHN Junwhan, C Kiyoung, W Seo US Patent 10,255,182, 2019 | 7 | 2019 |
| ComPreEND: Computation pruning through predictive early negative detection for ReLU in a deep neural network accelerator N Kim, H Park, D Lee, S Kang, J Lee, K Choi IEEE Transactions on Computers 71 (7), 1537-1550, 2021 | 4 | 2021 |
| Making a better use of caches for GCN accelerators with feature slicing and automatic tile morphing M Yoo, J Song, J Lee, N Kim, Y Kim, J Lee IEEE Computer Architecture Letters 20 (2), 102-105, 2021 | 4 | 2021 |
| Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Accelerators M Yoo, J Song, H Lee, J Lee, N Kim, Y Kim, J Lee Proceedings of the International Conference on Parallel Architectures and …, 2022 | 3 | 2022 |
| Method of accelerating training process of neural network and neural network device thereof S Lee, P Hanmin, LEE Gunhee, N Kim, YU Joonsang, C Kiyoung US Patent App. 16/550,498, 2020 | 2 | 2020 |
| How much computation power do you need for near-data processing in cloud? N Kim, J Ahn, S Hong, H Chafi, K Choi Proc. ASBD, 2017 | 2 | 2017 |
| Memory device skipping refresh operation and operation method thereof M Kim, N Kim, D Kim, DH Kim, C Park, D Seo, W Shin, C Lee, J Ilguy, ... US Patent 11,610,624, 2023 | 1 | 2023 |
| Semiconductor device and electronic device including the same CM Lee, NH Kim, DJ Kim, MS Kim, DH Seo, WJ SHIN, YJ YU, IG Jung, ... US Patent 11,915,782, 2024 | | 2024 |
| Memory system, operating method of the same, and controller of memory device N Kim, D Kim, DH Kim, D Seo, J Song, I Choi US Patent App. 18/222,563, 2024 | | 2024 |
| Electronic device, operation method of host, operation method of memory module, and operation method of memory device W Shin, NH Kim, DJ Kim, DH Kim, D Seo, I Choi US Patent 11,887,692, 2024 | | 2024 |
| Memory device including address table and operating method for memory controller C Kim, T Ko, N Kim, DH Kim, B Kim, KIM Bobae, C Lee, K Cho, I Choi US Patent App. 18/140,974, 2023 | | 2023 |
| Memory device capable of outputting fail data in parallel bit test and memory system including the memory device D Kim, N Kim, DH Kim, D Seo, W Shin, I Choi US Patent 11,721,408, 2023 | | 2023 |
| Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator M Kim, N Kim, D Kim, DH Kim, C Park, D Seo, W Shin, C Lee, J Ilguy, ... US Patent 11,670,355, 2023 | | 2023 |
