Ravi Iyer
Ravi Iyer
Verified email at
Cited by
Cited by
Neural cache: Bit-serial in-cache acceleration of deep neural networks
C Eckert, X Wang, J Wang, A Subramaniyan, R Iyer, D Sylvester, ...
2018 ACM/IEEE 45Th annual international symposium on computer architecture …, 2018
CQoS: a framework for enabling QoS in shared caches of CMP platforms
R Iyer
Proceedings of the 18th annual international conference on Supercomputing …, 2004
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
A Jog, O Kayiran, N Chidambaram Nachiappan, AK Mishra, MT Kandemir, ...
ACM SIGPLAN Notices 48 (4), 395-406, 2013
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
A Jog, AK Mishra, C Xu, Y Xie, V Narayanan, R Iyer, CR Das
Proceedings of the 49th Annual Design Automation Conference, 243-252, 2012
QoS policies and architecture for cache/memory in CMP platforms
R Iyer, L Zhao, F Guo, R Illikkal, S Makineni, D Newell, Y Solihin, L Hsu, ...
ACM SIGMETRICS Performance Evaluation Review 35 (1), 25-36, 2007
TCP onloading for data center servers
G Regnier, S Makineni, I Illikkal, R Iyer, D Minturn, R Huggahalli, D Newell, ...
Computer 37 (11), 48-58, 2004
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource
LR Hsu, SK Reinhardt, R Iyer, S Makineni
Proceedings of the 15th international conference on Parallel architectures …, 2006
Orchestrated scheduling and prefetching for GPGPUs
A Jog, O Kayiran, AK Mishra, MT Kandemir, O Mutlu, R Iyer, CR Das
Proceedings of the 40th Annual International Symposium on Computer …, 2013
Direct cache access for high bandwidth network I/O
R Huggahalli, R Iyer, S Tetrick
32nd International Symposium on Computer Architecture (ISCA'05), 50-59, 2005
Modeling virtual machine performance: challenges and approaches
O Tickoo, R Iyer, R Illikkal, D Newell
ACM SIGMETRICS Performance Evaluation Review 37 (3), 55-60, 2010
Cache QoS: From concept to reality in the IntelŽ XeonŽ processor E5-2600 v3 product family
A Herdrich, E Verplanke, P Autee, R Illikkal, C Gianos, R Singhal, R Iyer
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
A framework for providing quality of service in chip multi-processors
F Guo, Y Solihin, L Zhao, R Iyer
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
A case for dynamic frequency tuning in on-chip networks
AK Mishra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, CR Das
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs
B Li, L Zhao, R Iyer, LS Peh, M Leddige, M Espig, SE Lee, D Newell
Journal of Parallel and Distributed Computing 71 (5), 700-713, 2011
Packet coalescing
S Makineni, R Iyer, D Minturn, S Sen, D Newell, L Zhao
US Patent 7,620,071, 2009
Performance and power optimization through data compression in network-on-chip architectures
R Das, AK Mishra, C Nicopoulos, D Park, V Narayanan, R Iyer, MS Yousif, ...
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
Characterization & analysis of a server consolidation benchmark
P Apparao, R Iyer, X Zhang, D Newell, T Adelmeyer
Proceedings of the fourth ACM SIGPLAN/SIGOPS international conference on …, 2008
Exploring DRAM cache architectures for CMP server platforms
L Zhao, R Iyer, R Illikkal, D Newell
2007 25th International Conference on Computer Design, 55-62, 2007
Architectural impact of secure socket layer on internet servers
K Kant, R Iyer, P Mohapatra
2012 IEEE 30th International Conference on Computer Design (ICCD), 27-34, 2012
CacheScouts: Fine-grain monitoring of shared caches in CMP platforms
L Zhao, R Iyer, R Illikkal, J Moses, S Makineni, D Newell
16th International Conference on Parallel Architecture and Compilation …, 2007
The system can't perform the operation now. Try again later.
Articles 1–20