| An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology DS Byeon, SS Lee, YH Lim, JS Park, WK Han, PS Kwak, DH Kim, ... ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 97 | 2005 |
| MRLoc: Mitigating Row-hammering based on memory Locality JM You, JS Yang Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 74 | 2019 |
| Expanding trace buffer observation window for in-system silicon debug through selective capture JS Yang, NA Touba 26th IEEE VLSI Test Symposium (vts 2008), 345-351, 2008 | 66 | 2008 |
| Automated selection of signals to observe for efficient silicon debug JS Yang, NA Touba 2009 27th IEEE VLSI Test Symposium, 79-84, 2009 | 60 | 2009 |
| Test point insertion with control points driven by existing functional flip-flops JS Yang, NA Touba, B Nadeau-Dostie IEEE Transactions on Computers 61 (10), 1473-1483, 2011 | 47 | 2011 |
| Self-repair logic for stacked memory architecture JS Yang, D Kobla, L Ju, D Zimmerman US Patent 9,136,021, 2015 | 41 | 2015 |
| Improved trace buffer observation via selective data capture using 2-D compaction for post-silicon debug JS Yang, NA Touba IEEE transactions on very large scale integration (VLSI) systems 21 (2), 320-328, 2012 | 36 | 2012 |
| Enhancing silicon debug via periodic monitoring JS Yang, NA Touba 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008 | 27 | 2008 |
| Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise system S Kim, JS Yang Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 26 | 2018 |
| DRIS-3: Deep neural network reliability improvement scheme in 3D die-stacked memory based on fault analysis JS Kim, JS Yang Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 22 | 2019 |
| -Canceling MISR Architectures for Output Response Compaction With Unknown Values JS Yang, NA Touba IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 21 | 2012 |
| Efficient function mapping in nanoscale crossbar architecture JS Yang, R Datta 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011 | 20 | 2011 |
| Test point insertion using functional flip-flops to drive control points JS Yang, B Nadeau-Dostie, NA Touba 2009 International Test Conference, 1-10, 2009 | 20 | 2009 |
| Pufsec: Device fingerprint-based security architecture for internet of things SY Park, S Lim, D Jeong, J Lee, JS Yang, HJ Lee IEEE INFOCOM 2017-IEEE Conference on Computer Communications, 1-9, 2017 | 19 | 2017 |
| ER-TCAM: A soft-error-resilient SRAM-based ternary content-addressable memory for FPGAs I Ullah, JS Yang, J Chung IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4 …, 2020 | 18 | 2020 |
| Dynamic trace signal selection for post-silicon validation K Han, JS Yang, JA Abraham 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | 18 | 2013 |
| PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code S Jeong, SY Kang, JS Yang 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 16 | 2020 |
| Bit-error rate improvement of TLC NAND Flash using state re-ordering IJ Chang, JS Yang ieice electronics express 9 (23), 1775-1779, 2012 | 16 | 2012 |
| Efficient trace signal selection for silicon debug by error transmission analysis JS Yang, NA Touba IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 16 | 2012 |
| Reliability enhanced heterogeneous phase change memory architecture for performance and energy efficiency T Kwon, M Imran, JS Yang IEEE Transactions on Computers 70 (9), 1388-1400, 2020 | 14 | 2020 |
