| A 16 MHz BW 75 dB DR CT ADC Compensated for More Than One Cycle Excess Loop Delay V Singh, N Krishnapura, S Pavan, B Vigraham, D Behera, N Nigania IEEE Journal of Solid-State Circuits 47 (8), 1884-1895, 2012 | 60 | 2012 |
| OpenCL performance evaluation on modern multicore CPUs JH Lee, N Nigania, H Kim, K Patel, H Kim Scientific Programming 2015, 4-4, 2016 | 38 | 2016 |
| Harmonica: An fpga-based data parallel soft core C Kersey, S Yalamanchili, H Kim, N Nigania, H Kim 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 4 | 2014 |
| HPerf: A Lightweight Profiler for Task Distribution on CPU+ GPU Platforms JH Lee, N Nigania, H Kim, B Brett Georgia Institute of Technology, 2015 | 1 | 2015 |
| FPGA prototyping of custom GPGPUs N Nigania Georgia Institute of Technology, 2014 | | 2014 |
