Hung-Ming Chen
Hung-Ming Chen
Verified email at g2.nctu.edu.tw - Homepage
Title
Cited by
Cited by
Year
Integrated floorplanning and interconnect planning
HM Chen, MDF Wong, H Zhou, FY Young, HH Yang, N Sherwani
Layout optimization in VLSI design, 1-18, 2001
1012001
Critical role of mitochondrial reactive oxygen species formation in visible laser irradiation-induced apoptosis in rat brain astrocytes (RBA-1)
MJ Jou, SB Jou, HM Chen, CH Lin, TI Peng
Journal of biomedical science 9 (6), 507-516, 2002
922002
Fast analog layout prototyping for nanometer design migration
YP Weng, HM Chen, TC Chen, PC Pan, CH Chen, WZ Chen
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 517-522, 2011
362011
Simultaneous power supply planning and noise avoidance in floorplan design
HM Chen, LD Huang, IM Liu, MDF Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
312005
Floorplanning with power supply noise avoidance
HM Chen, LD Huang, IM Liu, M Lai, DF Wong
Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003
302003
Integrated power supply planning and floorplanning
IM Liu, HM Chen, TL Chou, A Aziz, DF Wong
Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001
292001
Closing the gap between global and detailed placement: Techniques for improving routability
CK Wang, CC Huang, SSY Liu, CY Chin, ST Hu, WC Wu, HM Chen
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
262015
On optimizing scan testing power and routing cost in scan chain design
LC Hsu, HM Chen
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-456, 2006
252006
Esd protection structure for 3d ic
K Chen, MF Lai, HM Chen
US Patent App. 13/041,358, 2012
222012
Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping
KH Meng, PC Pan, HM Chen
2011 12th International Symposium on Quality Electronic Design, 1-8, 2011
202011
On construction low power and robust clock tree via slew budgeting
YC Chang, CK Wang, HM Chen
Proceedings of the 2012 ACM international symposium on International …, 2012
192012
I/O clustering in design cost and performance optimization for flip-chip design
HM Chen, IM Liu, MDF Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
182006
Fast flip-chip pin-out designation respin for package-board codesign
RJ Lee, HM Chen
IEEE transactions on very large scale integration (VLSI) systems 17 (8 …, 2009
172009
A fast prototyping framework for analog layout migration with planar preservation
PC Pan, CY Chin, HM Chen, TC Chen, CC Lee, JC Lin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
162015
Configurable analog routing methodology via technology and design constraint unification
PC Pan, HM Chen, YK Cheng, J Liu, WY Hu
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 620-626, 2012
162012
On routing fixed escaped boundary pins for high speed boards
TY Tsai, RJ Lee, CY Chin, CY Kuan, HM Chen, Y Kajitani
2011 Design, Automation & Test in Europe, 1-6, 2011
162011
An implementation of performance-driven block and I/O placement for chip-package codesign
MF Lai, HM Chen
9th International Symposium on Quality Electronic Design (isqed 2008), 604-607, 2008
162008
ACER: An agglomerative clustering based electrode addressing and routing algorithm for pin-constrained EWOD chips
SSY Liu, CH Chang, HM Chen, TY Ho
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
152014
Method of fast analog layout migration
T Chen, H Chen, Y Weng
US Patent 8,607,182, 2013
152013
Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization
SSY Liu, WT Lo, CJ Lee, HM Chen
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (3 …, 2013
152013
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