| Integrated floorplanning and interconnect planning HM Chen, MDF Wong, H Zhou, FY Young, HH Yang, N Sherwani Layout optimization in VLSI design, 1-18, 2001 | 106 | 2001 |
| Fast analog layout prototyping for nanometer design migration YP Weng, HM Chen, TC Chen, PC Pan, CH Chen, WZ Chen 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 517-522, 2011 | 43 | 2011 |
| On optimizing scan testing power and routing cost in scan chain design LC Hsu, HM Chen 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-456, 2006 | 33 | 2006 |
| Floorplanning with power supply noise avoidance HM Chen, LD Huang, IM Liu, M Lai, DF Wong Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 33 | 2003 |
| Simultaneous power supply planning and noise avoidance in floorplan design HM Chen, LD Huang, IM Liu, MDF Wong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 32 | 2005 |
| Closing the gap between global and detailed placement: Techniques for improving routability CK Wang, CC Huang, SSY Liu, CY Chin, ST Hu, WC Wu, HM Chen Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015 | 29 | 2015 |
| Esd protection structure for 3d ic KN Chen, MF Lai, HM Chen US Patent App. 13/041,358, 2012 | 29 | 2012 |
| Integrated power supply planning and floorplanning IM Liu, HM Chen, TL Chou, A Aziz, DF Wong Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001 | 28 | 2001 |
| Configurable analog routing methodology via technology and design constraint unification PC Pan, HM Chen, YK Cheng, J Liu, WY Hu Proceedings of the International Conference on Computer-Aided Design, 620-626, 2012 | 27 | 2012 |
| Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping KH Meng, PC Pan, HM Chen 2011 12th International Symposium on Quality Electronic Design, 1-8, 2011 | 26 | 2011 |
| A fast prototyping framework for analog layout migration with planar preservation PC Pan, CY Chin, HM Chen, TC Chen, CC Lee, JC Lin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 23 | 2015 |
| Analog placement with current flow and symmetry constraints using PCP-SP A Patyal, PC Pan, HM Chen, HY Chi, CN Liu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 21 | 2018 |
| Fast flip-chip pin-out designation respin for package-board codesign RJ Lee, HM Chen IEEE transactions on very large scale integration (VLSI) systems 17 (8 …, 2009 | 21 | 2009 |
| Flexible droplet routing in active matrix–based digital microfluidic biochips GR Lu, CH Kuo, KC Chiang, A Banerjee, BB Bhattacharya, TY Ho, ... ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (3 …, 2018 | 20 | 2018 |
| Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization SSY Liu, WT Lo, CJ Lee, HM Chen ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (3 …, 2013 | 19 | 2013 |
| On construction low power and robust clock tree via slew budgeting YC Chang, CK Wang, HM Chen Proceedings of the 2012 ACM international symposium on International …, 2012 | 19 | 2012 |
| A learning-based methodology for routability prediction in placement LC Chen, CC Huang, YL Chang, HM Chen 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2018 | 18 | 2018 |
| On routing fixed escaped boundary pins for high speed boards TY Tsai, RJ Lee, CY Chin, CY Kuan, HM Chen, Y Kajitani 2011 Design, Automation & Test in Europe, 1-6, 2011 | 18 | 2011 |
| I/O clustering in design cost and performance optimization for flip-chip design HM Chen, IM Liu, MDF Wong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 18 | 2006 |
| ACER: An agglomerative clustering based electrode addressing and routing algorithm for pin-constrained EWOD chips SSY Liu, CH Chang, HM Chen, TY Ho IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 17 | 2014 |
