| A wide-range, high-resolution, compact, CMOS time to digital converter V Ramakrishnan, PT Balsara 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 125 | 2006 |
| Highly integrated scalable, flexible DSP megamodule architecture TD Anderson, J Zbiciak, DQ Bui, AA Chachad, K Chirca, N Bhoria, ... US Patent 9,606,803, 2017 | 118 | 2017 |
| NEM relay-based sequential logic circuits for low-power design R Venkatasubramanian, SK Manohar, PT Balsara IEEE transactions on nanotechnology 12 (3), 386-398, 2013 | 36 | 2013 |
| A 65nm C64x+ multi-core DSP platform for communications infrastructure S Agarwala, A Rajagopal, A Hill, M Joshi, S Mullinnix, T Anderson, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 35 | 2007 |
| Requester based transaction status reporting in a system with multi-level memory R Damodaran, AA Chachad, R Venkatasubramanian, ... US Patent 8,732,416, 2014 | 27 | 2014 |
| Highly integrated scalable, flexible DSP megamodule architecture TD Anderson, J Zbiciak, DQ Bui, AA Chachad, K Chirca, N Bhoria, ... US Patent 10,162,641, 2018 | 25 | 2018 |
| A 1.25 ghz 0.8 w c66x dsp core in 40nm cmos R Damodaran, T Anderson, S Agarwala, R Venkatasubramanian, M Gill, ... 2012 25th International Conference on VLSI Design, 286-291, 2012 | 25 | 2012 |
| Hiding page translation miss latency in program memory controller by selective page miss translation prefetch R Venkatasubramanian, O Olorode, BPH Ramaprasad US Patent 9,514,059, 2016 | 21 | 2016 |
| Hybrid NEMS-CMOS DC-DC converter for improved area and power efficiency SK Manohar, R Venkatasubramanian, PT Balsara 2012 25th International Conference on VLSI Design, 221-226, 2012 | 14 | 2012 |
| Using L1 cache as re-order buffer R Venkatasubramanian, O Olorode, H Ong US Patent 9,471,320, 2016 | 12 | 2016 |
| Ultra low power high efficiency charge pump design using NEM relays R Venkatasubramanian, SK Manohar, PT Balsara 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 10 | 2011 |
| Lookahead priority collection to support priority elevation AA Chachad, R Damodaran, R Venkatasubramanian, JRM Zbiciak US Patent 10,713,180, 2020 | 8 | 2020 |
| Integer and half clock step division digital variable clock divider R Venkatasubramanian, A Lell, R Damodaran US Patent 8,532,247, 2013 | 8 | 2013 |
| Bidirectional single-supply level shifter with wide voltage range for efficient power management SK Manohar, VK Somasundar, R Venkatasubramanian, PT Balsara 2012 25th International Conference on VLSI Design, 125-130, 2012 | 8 | 2012 |
| A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA Z Nikolic, R Venkatasubramanian, JAT Jones, P Labaziewicz 2015 IEEE Hot Chips 27 Symposium (HCS), 1-32, 2015 | 7 | 2015 |
| Heterogeneous nems-cmos dcm buck regulator for improved area and enhanced power efficiency SK Manohar, R Venkatasubramanian, PT Balsara IEEE Transactions on Nanotechnology 14 (1), 140-151, 2014 | 7 | 2014 |
| Clock control of pipelined memory for improved delay fault testing R Venkatasubramanian, S Kale, AA Chachad US Patent 8,694,843, 2014 | 6 | 2014 |
| NEM relay based memory architectures for low power design R Venkatasubramanian, SK Manohar, V Paduvalli, PT Balsara 2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO), 1-5, 2012 | 6 | 2012 |
| Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop R Venkatasubramanian, SK Manohar, PT Balsara 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 37-44, 2011 | 6 | 2011 |
| Highly integrated scalable, flexible DSP megamodule architecture TD Anderson, J Zbiciak, DQ Bui, A Chachad, K Chirca, N Bhoria, ... US Patent 11,036,648, 2021 | 5 | 2021 |
