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Angshuman Parashar
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SCNN: An accelerator for compressed-sparse convolutional neural networks
A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ...
ACM SIGARCH computer architecture news 45 (2), 27-40, 2017
13762017
Timeloop: A systematic approach to dnn accelerator evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
2019 IEEE international symposium on performance analysis of systems and …, 2019
3952019
Sparse convolutional neural network accelerator
WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison
US Patent 10,891,538, 2021
3302021
Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach
H Kwon, P Chatarasi, M Pellauer, A Parashar, V Sarkar, T Krishna
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
2872019
Sparse convolutional neural network accelerator
WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison
US Patent 10,528,864, 2020
2452020
Sparse convolutional neural network accelerator
WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison
US Patent 10,860,922, 2020
1962020
Triggered instructions: A control paradigm for spatially-programmed architectures
A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ...
ACM SIGARCH Computer Architecture News 41 (3), 142-153, 2013
1552013
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
M Pellauer, M Adler, M Kinsy, A Parashar, J Emer
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
1512011
Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings
H Kwon, P Chatarasi, V Sarkar, T Krishna, M Pellauer, A Parashar
IEEE micro 40 (3), 20-29, 2020
1492020
Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, and Joel Emer. 2019. Timeloop: A Systematic …
A Parashar, P Raina
2019 IEEE international symposium on performance analysis of systems and …, 2019
1462019
Leap scratchpads: automatic memory and cache management for reconfigurable logic
M Adler, KE Fleming, A Parashar, M Pellauer, J Emer
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
1282011
Mind mappings: enabling efficient algorithm-accelerator mapping space search
K Hegde, PA Tsai, S Huang, V Chandra, A Parashar, CW Fletcher
Proceedings of the 26th ACM International Conference on Architectural …, 2021
862021
Mechanisms for bounding vulnerabilities of processor structures
NK Soundararajan, A Parashar, A Sivasubramaniam
Proceedings of the 34th annual international symposium on Computer …, 2007
812007
Leveraging latency-insensitivity to ease multiple FPGA design
KE Fleming, M Adler, M Pellauer, A Parashar, A Mithal, J Emer
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
772012
SlicK: slice-based locality exploitation for efficient redundant multithreading
A Parashar, A Sivasubramaniam, S Gurumurthi
ACM SIGOPS Operating Systems Review 40 (5), 95-105, 2006
742006
A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy
A Parashar, S Gurumurthi, A Sivasubramaniam
ACM SIGARCH Computer Architecture News 32 (2), 376, 2004
722004
Executing distributed memory operations using processing elements connected by distributed channels
B Ahsan, MC Adler, NC Crago, JS Emer, A Jaleel, A Parashar, ...
US Patent 10,331,583, 2019
552019
Efficient control and communication paradigms for coarse-grained spatial architectures
M Pellauer, A Parashar, M Adler, B Ahsan, R Allmon, N Crago, K Fleming, ...
ACM Transactions on Computer Systems (TOCS) 33 (3), 1-32, 2015
532015
Efficient spatial processing element control via triggered instructions
A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ...
IEEE Micro 34 (3), 120-137, 2014
512014
Sparse convolutional neural network accelerator
WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison
US Patent 10,997,496, 2021
502021
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