| Design and implementation of 16 tap FIR filter for DSP applications NS Rai, P Shree, YP Meghana, AP Chavan, HVR Aradhya 2018 Second International Conference on Advances in Electronics, Computers …, 2018 | 26 | 2018 |
| An electronic smart jacket for the navigation of visually impaired society B Siddhartha, AP Chavan, BV Uma Materials Today: Proceedings 5 (4), 10665-10669, 2018 | 21 | 2018 |
| Design of low power & high performance multi source H-tree clock distribution network VG Srivatsa, AP Chavan, D Mourya 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 468-473, 2020 | 15 | 2020 |
| High speed 32-bit vedic multiplier for DSP applications AP Chavan, R Verma, NS Bhat international journal of Computer applications 135 (7), 35-38, 2016 | 13 | 2016 |
| Ultra-low power, area efficient and high-speed voltage level shifter based on wilson current mirror AP Chavan 2021 IEEE Mysore Sub Section International Conference (MysuruCon), 108-113, 2021 | 8 | 2021 |
| IoT enabled real-time availability and condition monitoring of CNC machines B Siddhartha, AP Chavan, GK HD, KN Subramanya 2020 IEEE International Conference on Internet of Things and Intelligence …, 2021 | 7 | 2021 |
| Design and integration of lane departure warning, adaptive headlight and wiper system for automobile safety G Vijay, MN Ramanarayan, AP Chavan 2019 4th International Conference on Recent Trends on Electronics …, 2019 | 6 | 2019 |
| Improved Fault Tolerant Sparse Kogge Stone Adder MB Kondalkar, AP Chavan, P Narashimaraja International Journal of Computer Applications 75 (10), 36-41, 2013 | 6 | 2013 |
| An Efficient Design of 3bit and 4bit Flash ADC A PChavan, P Narashimaraja International Journal of Computer Applications 61 (11), 32-37, 2013 | 6 | 2013 |
| Design of a 1.5-V 4-bit Flash ADC using 90nm Technology AP Chavan, G Rekha, P Narashimaraja International Journal of Engineering and Advanced Technology (IJEAT) 2 (2 …, 2012 | 6 | 2012 |
| Design and Synthesis of Low Power, High Speed 5th Order Digital Decimation Filter for Sigma- Delta Analog to Digital Converter AP Chavan, HVR Aradhya 2020 International Conference on Communication and Signal Processing (ICCSP …, 2020 | 4 | 2020 |
| Design and Verification of ECC Scheme to optimize area and tester time in OTP ROM Controller H Divva, AP Chavan, S Krishnamurthy 2019 4th International Conference on Recent Trends on Electronics …, 2019 | 4 | 2019 |
| VLSI Implementation of Split-radix FFT for High Speed Applications A Chavan, K Sowmya, S Mishra International Journal of Computer Applications 157 (7), 22-26, 2017 | 4 | 2017 |
| Design of pulse detectors and unsigned sequential multiplier using reversible logic AP Chavan, P Pawar, R Varun International Journal of Computer Applications 92 (4), 2014 | 4 | 2014 |
| Subthreshold adiabatic logic (SAL) based building blocks for combinational system design KG Ranjith, AKP Chavan, HVR Aradhya 2017 2nd IEEE International Conference on Recent Trends in Electronics …, 2017 | 3 | 2017 |
| Design of low power and energy efficient 5× 5 multipliers A Vallamdas, AP Chavan, S Jagannathan International Conference on Recent Advances and Innovations in Engineering …, 2014 | 3 | 2014 |
| A 1.5 v 3 bit, 500MS/s Low Power CMOS Flash ADC M Devi, AP Chavan, DKN Murlidhara International Journal Of Engineering And Computer Science ISSN, 2319-7242, 0 | 2 | |
| Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillator AP Chavan, R Aradhya International Journal of Electrical and Computer Engineering (IJECE) 13 (4 …, 2023 | 1 | 2023 |
| Design and Optimization of Timing Errors on Swapping of Threshold Voltage B Saurab, AP Chavan 2021 IEEE Mysore Sub Section International Conference (MysuruCon), 687-691, 2021 | 1 | 2021 |
| Design and implementation of automated industrial robots in cylinder liner production lines RA Viji, AP Chavan, P Chaurasia, R Preetham, HVR Aradhya 2021 Asian Conference on Innovation in Technology (ASIANCON), 1-7, 2021 | 1 | 2021 |
