| A 2.4-GHz 20–40-MHz channel WLAN digital outphasing transmitter utilizing a delay-based wideband phase modulator in 32-nm CMOS A Ravi, P Madoglio, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ... IEEE Journal of Solid-State Circuits 47 (12), 3184-3196, 2012 | 108 | 2012 |
| A 20dBm 2.4 GHz digital outphasing transmitter for WLAN application in 32nm CMOS P Madoglio, A Ravi, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ... 2012 IEEE International Solid-State Circuits Conference, 168-170, 2012 | 60 | 2012 |
| 13.6 A 2.4 GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications P Madoglio, H Xu, K Chandrashekar, L Cuellar, M Faisal, WY Li, HS Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 226-227, 2017 | 57 | 2017 |
| A 2.4 GHz WLAN transceiver with fully-integrated highly-linear 1.8 V 28.4 dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS Y Tan, J Duster, CT Fu, E Alpman, A Balankutty, C Lee, A Ravi, ... 2012 Symposium on VLSI Circuits (VLSIC), 76-77, 2012 | 25 | 2012 |
| A 10 b 50 MS/s opamp-sharing pipeline A/D with current-reuse OTAs K Chandrashekar, B Bakkaloglu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (9 …, 2010 | 25 | 2010 |
| A digital fractional-N PLL with a PVT and mismatch insensitive TDC utilizing equivalent time sampling technique HS Kim, C Ornelas, K Chandrashekar, D Shi, P Su, P Madoglio, WY Li, ... IEEE Journal of Solid-State Circuits 48 (7), 1721-1729, 2013 | 24 | 2013 |
| A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management K Chandrashekar, S Pellerano, P Madoglio, A Ravi, Y Palaskas 2012 IEEE International Solid-State Circuits Conference, 352-354, 2012 | 24 | 2012 |
| Re-circulating time-to-digital converter (TDC) HS Kim, A Ravi, WY Li, K Chandrashekar US Patent 9,197,402, 2015 | 23 | 2015 |
| Re-circulating time-to-digital converter (TDC) HS Kim, A Ravi, WY Li, K Chandrashekar US Patent 9,197,402, 2015 | 23 | 2015 |
| Segmented digital-to-time converter calibration G Palaskas, P Madoglio, S Pellerano, A Ravi, K Chandrashekar US Patent 9,209,958, 2015 | 22 | 2015 |
| Segmented digital-to-time converter calibration G Palaskas, P Madoglio, S Pellerano, A Ravi, K Chandrashekar US Patent 9,209,958, 2015 | 22 | 2015 |
| A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS S Kundu, L Chai, K Chandrashekar, S Pellerano, BR Carlton IEEE Journal of Solid-State Circuits, 2020 | 21 | 2020 |
| A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling K Chandrashekar, M Corsi, J Fattaruso, B Bakkaloglu IEEE Transactions on Circuits and Systems II: Express Briefs 57 (8), 602-606, 2010 | 17 | 2010 |
| 25.5 A Self-Calibrated 1.2-to-3.8 GHz 0.0052 mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS S Kundu, L Chai, K Chandrashekar, S Pellerano, B Carlton 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 276-278, 2020 | 13 | 2020 |
| Digital fractional frequency divider K Chandrashekar, S Pellerano US Patent 9,013,213, 2015 | 11 | 2015 |
| Digital fractional frequency divider K Chandrashekar, S Pellerano US Patent 9,013,213, 2015 | 11 | 2015 |
| Digital fractional frequency divider K Chandrashekar, S Pellerano US Patent 9,013,213, 2015 | 11 | 2015 |
| A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision T Copani, B Vermeire, A Jain, H Karaki, K Chandrashekar, S Goswami, ... 2008 IEEE Custom Integrated Circuits Conference, 359-362, 2008 | 10 | 2008 |
| A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs K Chandrashekar, B Bakkaloglu 2009 IEEE Custom Integrated Circuits Conference, 263-266, 2009 | 9 | 2009 |
| Redundant delay digital-to-time converter S Henzler, M Schimper, P Madoglio, S Pellerano, K Chandrashekar US Patent 9,130,588, 2015 | 7 | 2015 |
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