Chadwin D. Young
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Dipole model explaining high-/metal gate field effect transistor threshold voltage tuning
PD Kirsch, P Sivasubramani, J Huang, CD Young, MA Quevedo-Lopez, ...
Applied Physics Letters 92 (9), 092901, 2008
The effect of interfacial layer properties on the performance of Hf-based gate stack devices
G Bersuker, CS Park, J Barnett, PS Lysaght, PD Kirsch, CD Young, ...
Journal of Applied Physics 100 (9), 094108, 2006
Large ferroelectric polarization of TiN/Hf0.5Zr0.5O2/TiN capacitors due to stress-induced crystallization at low thermal budget
SJ Kim, D Narayan, JG Lee, J Mohan, JS Lee, J Lee, HS Kim, YC Byun, ...
Applied Physics Letters 111 (24), 242901, 2017
Mechanism of Electron Trapping and Characteristics of Traps in Gate Stacks
G Bersuker, JH Sim, CS Park, CD Young, SV Nadkarni, R Choi, BH Lee
IEEE Transactions on Device and Materials Reliability 7 (1), 138-145, 2007
High-k gate stacks for planar, scaled CMOS integrated circuits
HR Huff, A Hou, C Lim, Y Kim, J Barnett, G Bersuker, GA Brown, ...
Microelectronic Engineering 69 (2-4), 152-167, 2003
Conventional n-Channel MOSFET Devices Using Single Layer HfO~ 2 and ZrO~ 2 as High-k Gate Dielectrics with Polysilicon Gate Electrode
Y Kim, G Gebara, M Freiler, J Barnett, D Riley, J Chen, K Torres, JE Lim, ...
International Electron Devices Meeting, 455-458, 2001
Effect of film thickness on the ferroelectric and dielectric properties of low-temperature (400 C) Hf0.5Zr0.5O2 films
SJ Kim, J Mohan, J Lee, JS Lee, AT Lucero, CD Young, L Colombo, ...
Applied Physics Letters 112 (17), 172902, 2018
Interfacial layer-induced mobility degradation in high-k transistors
G Bersuker, J Barnett, N Moumen, B Foran, CD Young, P Lysaght, ...
Japanese Journal of Applied Physics 43 (11S), 7899, 2004
Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric
G Bersuker, D Heh, C Young, H Park, P Khanal, L Larcher, A Padovani, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Electron trap generation in high-/spl kappa/gate stacks by constant voltage stress
CD Young, D Heh, SV Nadkarni, R Choi, JJ Peterson, J Barnett, BH Lee, ...
IEEE Transactions on Device and Materials Reliability 6 (2), 123-131, 2006
Effect of Pre-Existing Defects on Reliability Assessment of High-K
G Bersuker, JH Sim, CD Young, R Choi, PM Zeitzoff
Microelectronics Reliability 44, 1509-1512, 2004
Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)
BH Lee, CD Young, R Choi, JH Sim, G Bersuker, CY Kang, R Harris, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004…, 2004
Spatial distributions of trapping centers in gate stacks
D Heh, CD Young, GA Brown, PY Hung, A Diebold, G Bersuker, EM Vogel, ...
Applied physics letters 88 (15), 152907, 2006
Dipole Moment Model Explaining nFET Vt Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics
P Sivasubramani, TS Boscke, J Huang, CD Young, PD Kirsch, ...
2007 IEEE Symposium on VLSI Technology, 68-69, 2007
Effects of ALD HfO2 thickness on charge trapping and mobility
JH Sim, SC Song, PD Kirsch, CD Young, R Choi, DL Kwong, BH Lee, ...
Microelectronic Engineering 80, 218-221, 2005
Experimental Evidence of the Fast and Slow Charge Trapping/Detrapping Processes in High- k Dielectrics Subjected to PBTI Stress
D Heh, CD Young, G Bersuker
IEEE electron device letters 29 (2), 180-182, 2008
Ultra-short pulse current–voltage characterization of the intrinsic characteristics of high-κ devices
CD Young, Y Zhao, M Pendley, BH Lee, K Matthews, JH Sim, R Choi, ...
Japanese journal of applied physics 44 (4S), 2437, 2005
Pulsed Methodology and Its Application to Electron-Trapping Characterization and Defect Density Profiling
CD Young, Y Zhao, D Heh, R Choi, BH Lee, G Bersuker
IEEE Transactions on electron devices 56 (6), 1322-1329, 2009
Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance–voltage analysis
P Zhao, A Khosravi, A Azcatl, P Bolshakov, G Mirabelli, E Caruso, ...
2D Materials 5 (3), 031002, 2018
Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application
J Huang, D Heh, P Sivasubramani, PD Kirsch, G Bersuker, DC Gilmer, ...
2009 Symposium on VLSI Technology, 34-35, 2009
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