| A 16-mW 78-dB SNDR 10-MHz BW CTADC Using Residue-Cancelling VCO-Based Quantizer K Reddy, S Rao, R Inti, B Young, A Elshazly, M Talegaonkar, ... IEEE journal of solid-state circuits 47 (12), 2916-2927, 2012 | 226 | 2012 |
| A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC A Elkholy, T Anand, WS Choi, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (4), 867-881, 2015 | 145 | 2015 |
| Clock multiplication techniques using digital multiplying delay-locked loops A Elshazly, R Inti, B Young, PK Hanumolu IEEE Journal of Solid-State Circuits 48 (6), 1416-1428, 2013 | 119 | 2013 |
| A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance R Inti, W Yin, A Elshazly, N Sasidhar, PK Hanumolu Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 …, 2011 | 114 | 2011 |
| A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation S Rao, B Young, A Elshazly, W Yin, N Sasidhar, PK Hanumolu 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 270-271, 2011 | 110 | 2011 |
| A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS J Kim, A Balankutty, A Elshazly, YY Huang, H Song, K Yu, F O'Mahony 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 106 | 2015 |
| A noise-shaping time-to-digital converter using switched-ring oscillators—Analysis, design, and measurement techniques A Elshazly, S Rao, B Young, PK Hanumolu IEEE Journal of Solid-State Circuits 49 (5), 1184-1197, 2014 | 96 | 2014 |
| A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, 2015 | 90 | 2015 |
| A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking W Yin, R Inti, A Elshazly, B Young, PK Hanumolu IEEE Journal of Solid-State Circuits 46 (8), 1870-1880, 2011 | 85 | 2011 |
| A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, 2015 | 77 | 2015 |
| High frequency buck converter design using time-based control techniques SJ Kim, Q Khan, M Talegaonkar, A Elshazly, A Rao, N Griesert, G Winter, ... IEEE Journal of Solid-State Circuits 50 (4), 990-1001, 2014 | 74 | 2014 |
| A 2.0–5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 51 (8), 1771-1784, 2016 | 73 | 2016 |
| A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS J Kim, A Balankutty, R Dokania, A Elshazly, HS Kim, S Kundu, S Weaver, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 102-104, 2018 | 68 | 2018 |
| A 112 Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with three-tap FFE in 10-nm FinFET J Kim, A Balankutty, RK Dokania, A Elshazly, HS Kim, S Kundu, D Shi, ... IEEE Journal of Solid-State Circuits 54 (1), 29-42, 2018 | 67 | 2018 |
| A reference-less clock and data recovery circuit using phase-rotating phase-locked loop G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of Solid-State Circuits 49 (4), 1036-1047, 2014 | 64 | 2014 |
| A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators A Elshazly, S Rao, B Young, PK Hanumolu 2012 IEEE international solid-state circuits conference, 464-466, 2012 | 59 | 2012 |
| A 2.4 ps resolution 2.1 mW second-order noise-shaped time-to-digital converter with 3.2 ns range in 1MHz bandwidth B Young, S Kwon, A Elshazly, PK Hanumolu IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 57 | 2010 |
| A 75dB DR 50MHz BW 3rdorder CT-ΔΣ modulator using VCO-based integrators B Young, K Reddy, S Rao, A Elshazly, T Anand, PK Hanumolu 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 47 | 2014 |
| A 20-to-1000MHz±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 47 | 2014 |
| A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 47 | 2014 |
