David Koufaty
David Koufaty
Senior Principal Engineer, Intel Labs
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Cited by
Cited by
Hyper-Threading Technology Architecture and Microarchitecture.
DT Marr, F Binns, DL Hill, G Hinton, DA Koufaty, JA Miller, M Upton
Intel Technology Journal 6 (1), 2002
Understanding intrinsic characteristics and system implications of flash memory based solid state drives
F Chen, DA Koufaty, X Zhang
ACM SIGMETRICS Performance Evaluation Review 37 (1), 181-192, 2009
Hystor: Making the best use of solid state drives in high performance storage systems
F Chen, DA Koufaty, X Zhang
Proceedings of the international conference on Supercomputing, 22-32, 2011
Bias scheduling in heterogeneous multi-core architectures
D Koufaty, D Reddy, S Hahn
Proceedings of the 5th European conference on Computer systems, 125-138, 2010
Efficient operating system scheduling for performance-asymmetric multi-core architectures
T Li, D Baumberger, DA Koufaty, S Hahn
Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 1-11, 2007
Hyperthreading technology in the netburst microarchitecture
D Koufaty, DT Marr
IEEE Micro 23 (2), 56-65, 2003
Operating system support for overlapping-ISA heterogeneous multi-core architectures
T Li, P Brett, R Knauerhase, D Koufaty, D Reddy, S Hahn
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
Method and apparatus for suspending execution of a thread until a specified memory access occurs
D Rodgers, DT Marr, DL Hill, S Kaushik, JB Crossland, DA Koufaty
US Patent 7,363,474, 2008
Data forwarding in scalable shared-memory multiprocessors
DA Koufaty, X Chen, DK Poulsen, J Torrellas
Proceedings of the 9th International Conference on Supercomputing, 255-264, 1995
QuickIA: Exploring heterogeneous architectures on real prototypes
N Chitlur, G Srinivasa, S Hahn, PK Gupta, D Reddy, D Koufaty, P Brett, ...
IEEE International Symposium on High-Performance Comp Architecture, 1-8, 2012
Coherency techniques for suspending execution of a thread until a specified memory access occurs
DL Hill, DT Marr, D Rodgers, S Kaushik, JB Crossland, DA Koufaty
US Patent 7,127,561, 2006
Managing Interrupts in a Partitioned Platform
B Vembu, JA Vargas, J Ajanovic, U Warrier, D Koufaty
US Patent App. 11/535,769, 2008
The Forgotten {‘Uncore’}: On the {Energy-Efficiency} of Heterogeneous Cores
V Gupta, P Brett, D Koufaty, D Reddy, S Hahn, K Schwan, G Srinivasa
2012 USENIX Annual Technical Conference (USENIX ATC 12), 367-372, 2012
Hetergeneous processor apparatus and method
P Narvaez, GN Srinivasa, E Gorbatov, DR Subbareddy, M Naik, A Naveh, ...
US Patent 9,329,900, 2016
Leveraging core specialization via OS scheduling to improve performance on asymmetric multicore systems
JC Saez, A Fedorova, D Koufaty, M Prieto
ACM Transactions on Computer Systems (TOCS) 30 (2), 1-38, 2012
Suspending execution of a thread in a multi-threaded processor
D Marr, D Rodgers, D Hill, S Kaushik, J Crossland, D Koufaty
US Patent App. 10/039,777, 2003
Migrating tasks between asymmetric computing elements of a multi-core processor
A Naveh, Y Yosef, E Weissmann, A Aggarwal, E Rotem, A Mendelson, ...
US Patent 10,185,566, 2019
Thread migration support for architectually different cores
M Naik, GN Srinivasa, A Naveh, IM Sodhi, P Narvaez, E Gorbatov, ...
US Patent App. 13/997,811, 2014
Providing an asymmetric multicore processor system transparently to an operating system
B Ginzburg, I Osadchiy, R Ronen, E Weissmann, M Mishaeli, A Naveh, ...
US Patent 9,720,730, 2017
Access control for memory protection key architecture
DA Koufaty, RL Sahita
US Patent 9,910,611, 2018
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