Abhishek Bhattacharjee
Abhishek Bhattacharjee
Associate Professor of Computer Science, Yale University
cs.yale.edu의 이메일 확인됨 - 홈페이지
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Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
A Bhattacharjee, M Martonosi
ACM SIGARCH Computer Architecture News 37 (3), 290-301, 2009
2312009
CoScale: Coordinating CPU and memory system DVFS in server systems
Q Deng, D Meisner, A Bhattacharjee, TF Wenisch, R Bianchini
2012 45th annual IEEE/ACM international symposium on microarchitecture, 143-154, 2012
2212012
Colt: Coalesced large-reach tlbs
B Pham, V Vaidyanathan, A Jaleel, A Bhattacharjee
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 258-269, 2012
1742012
Shared last-level TLBs for chip multiprocessors
A Bhattacharjee, D Lustig, M Martonosi
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
1642011
Architectural Support for Address Translation on GPUs
B Pichai, L Hsu, A Bhattacharjee
157*2014
Inter-core cooperative TLB for chip multiprocessors
A Bhattacharjee, M Martonosi
ACM Sigplan Notices 45 (3), 359-370, 2010
1322010
Large-reach memory management unit caches
A Bhattacharjee
Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013
1312013
Increasing TLB reach by exploiting clustering in page translations
B Pham, A Bhattacharjee, Y Eckert, GH Loh
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
1272014
Characterizing the TLB behavior of emerging parallel workloads on chip multiprocessors
A Bhattacharjee, M Martonosi
2009 18th International Conference on Parallel Architectures and Compilation …, 2009
1212009
Large pages and lightweight memory management in virtualized environments: Can you have it both ways?
B Pham, J Veselý, GH Loh, A Bhattacharjee
Proceedings of the 48th International Symposium on Microarchitecture, 1-12, 2015
902015
MultiScale: memory system DVFS with multiple memory controllers
Q Deng, D Meisner, A Bhattacharjee, TF Wenisch, R Bianchini
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
882012
Observations and opportunities in architecting shared virtual memory for heterogeneous systems
J Vesely, A Basu, M Oskin, GH Loh, A Bhattacharjee
2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016
832016
Efficient address translation for architectures with multiple page sizes
G Cox, A Bhattacharjee
ACM SIGPLAN Notices 52 (4), 435-448, 2017
812017
TLB improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level TLBs
D Lustig, A Bhattacharjee, M Martonosi
ACM Transactions on Architecture and Code Optimization (TACO) 10 (1), 1-38, 2013
772013
Full-system chip multiprocessor power evaluations using FPGA-based emulation
A Bhattacharjee, G Contreras, M Martonosi
Proceedings of the 2008 international symposium on Low Power Electronics …, 2008
612008
COATCheck: Verifying memory ordering at the hardware-OS interface
D Lustig, G Sethi, M Martonosi, A Bhattacharjee
ACM SIGPLAN Notices 51 (4), 233-247, 2016
522016
Translation-triggered prefetching
A Bhattacharjee
Proceedings of the Twenty-Second International Conference on Architectural …, 2017
452017
Parallelization libraries: Characterizing and reducing overheads
A Bhattacharjee, G Contreras, M Martonosi
ACM Transactions on Architecture and Code Optimization (TACO) 8 (1), 1-29, 2011
402011
Hardware translation coherence for virtualized systems
Z Yan, J Veselý, G Cox, A Bhattacharjee
Proceedings of the 44th Annual International Symposium on Computer …, 2017
342017
Nimble page management for tiered memory systems
Z Yan, D Lustig, D Nellans, A Bhattacharjee
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
322019
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