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Abhishek Bhattacharjee
Abhishek Bhattacharjee
Professor of Computer Science, Yale University
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Coscale: Coordinating cpu and memory system dvfs in server systems
Q Deng, D Meisner, A Bhattacharjee, TF Wenisch, R Bianchini
2012 45th annual IEEE/ACM international symposium on microarchitecture, 143-154, 2012
2732012
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
A Bhattacharjee, M Martonosi
ACM SIGARCH Computer Architecture News 37 (3), 290-301, 2009
2432009
Colt: Coalesced large-reach tlbs
B Pham, V Vaidyanathan, A Jaleel, A Bhattacharjee
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 258-269, 2012
2412012
Architectural Support for Address Translation on GPUs
B Pichai, L Hsu, A Bhattacharjee
197*2014
Shared last-level TLBs for chip multiprocessors
A Bhattacharjee, D Lustig, M Martonosi
2011 IEEE 17th International Symposium on High Performance Computer ¡¦, 2011
1872011
Increasing TLB reach by exploiting clustering in page translations
B Pham, A Bhattacharjee, Y Eckert, GH Loh
2014 IEEE 20th International Symposium on High Performance Computer ¡¦, 2014
1792014
Large-reach memory management unit caches
A Bhattacharjee
Proceedings of the 46th Annual IEEE/ACM International Symposium on ¡¦, 2013
1732013
Inter-core cooperative TLB for chip multiprocessors
A Bhattacharjee, M Martonosi
ACM Sigplan Notices 45 (3), 359-370, 2010
1502010
Efficient address translation for architectures with multiple page sizes
G Cox, A Bhattacharjee
ACM SIGPLAN Notices 52 (4), 435-448, 2017
1362017
Large pages and lightweight memory management in virtualized environments: Can you have it both ways?
B Pham, J Veselý, GH Loh, A Bhattacharjee
Proceedings of the 48th International Symposium on Microarchitecture, 1-12, 2015
1332015
Nimble page management for tiered memory systems
Z Yan, D Lustig, D Nellans, A Bhattacharjee
Proceedings of the Twenty-Fourth International Conference on Architectural ¡¦, 2019
1322019
Characterizing the TLB behavior of emerging parallel workloads on chip multiprocessors
A Bhattacharjee, M Martonosi
2009 18th International Conference on Parallel Architectures and Compilation ¡¦, 2009
1312009
Observations and opportunities in architecting shared virtual memory for heterogeneous systems
J Vesely, A Basu, M Oskin, GH Loh, A Bhattacharjee
2016 IEEE International Symposium on Performance Analysis of Systems and ¡¦, 2016
1132016
MultiScale: memory system DVFS with multiple memory controllers
Q Deng, D Meisner, A Bhattacharjee, TF Wenisch, R Bianchini
Proceedings of the 2012 ACM/IEEE international symposium on Low power ¡¦, 2012
1012012
TLB improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level TLBs
D Lustig, A Bhattacharjee, M Martonosi
ACM Transactions on Architecture and Code Optimization (TACO) 10 (1), 1-38, 2013
872013
Translation-triggered prefetching
A Bhattacharjee
Proceedings of the Twenty-Second International Conference on Architectural ¡¦, 2017
772017
Mind: In-network memory management for disaggregated data centers
S Lee, Y Yu, Y Tang, A Khandelwal, L Zhong, A Bhattacharjee
Proceedings of the ACM SIGOPS 28th Symposium on Operating Systems Principles ¡¦, 2021
672021
Scheduling page table walks for irregular GPU applications
S Shin, G Cox, M Oskin, GH Loh, Y Solihin, A Bhattacharjee, A Basu
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture ¡¦, 2018
662018
Full-system chip multiprocessor power evaluations using FPGA-based emulation
A Bhattacharjee, G Contreras, M Martonosi
Proceedings of the 2008 international symposium on Low Power Electronics ¡¦, 2008
662008
Translation ranger: Operating system support for contiguity-aware tlbs
Z Yan, D Lustig, D Nellans, A Bhattacharjee
Proceedings of the 46th International Symposium on Computer Architecture ¡¦, 2019
612019
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