Salil Mujumdar
Salil Mujumdar
Verified email at micron.com
TitleCited byYear
Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic applications
DK Mohata, R Bijesh, S Mujumdar, C Eaton, R Engel-Herbert, T Mayer, ...
2011 International Electron Devices Meeting, 33.5. 1-33.5. 4, 2011
1162011
Methods of forming gate structures for transistor devices for CMOS applications
Z Hong, S Tzeng, A Joshi, A Bodke, D Pisharoty, U Raghuram, O Karlsson, ...
US Patent 9,105,497, 2015
182015
Selector Elements
M Clark, P Phatak, C Chen, A Bodke, S Mujumdar, F Nardi, S Kahlon, ...
US Patent App. 15/287,091, 2017
142017
Layout-dependent strain optimization for p-channel trigate transistors
S Mujumdar, K Maitra, S Datta
IEEE Transactions on Electron Devices 59 (1), 72-78, 2011
142011
IEEE International Electron Devices Meeting
DK Mohata, R Bijesh, S Mujumdar, C Eaton, R Engel-Herbert, T Mayer, ...
Washington DC (December 2011), 2011
102011
Two Step Deposition of High-k Gate Dielectric Materials
K Kashefi, A Joshi, S Mujumdar
US Patent App. 14/083,761, 2015
82015
Atomic layer deposition of HfxAlyCz as a work function material in metal gate MOS devices
A Lee, N Fuchigami, D Pisharoty, Z Hong, E Haywood, A Joshi, ...
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 32 (1 …, 2014
72014
Correlated Flicker Noise and Hole Mobility Characteristics ofUniaxially Strained SiGe FINFETs
B Rajamohanan, I Ok, S Mujumdar, C Hobbs, P Majhi, R Jammy, S Datta
IEEE Electron Device Letters 33 (9), 1237-1239, 2012
72012
Transition metal aluminate and high k dielectric semiconductor stack
S Mujumdar
US Patent App. 13/723,853, 2014
62014
Processing and characterization of GaSb/high-k dielectric interfaces
E Hwang, C Eaton, S Mujumdar, H Madan, A Ali, D Bhatia, S Datta, ...
ECS Transactions 41 (5), 157-162, 2011
62011
3DNAND GIDL-assisted body biasing for erase enabling CMOS under array (CUA) architecture
C Caillat, K Beaman, A Bicksler, E Camozzi, T Ghilardi, G Huang, H Liu, ...
2017 IEEE International Memory Workshop (IMW), 1-4, 2017
52017
Methods of forming gate structures for transistor devices for cmos applications and the resulting products
Z Hong, S Tzeng, A Joshi, A Bodke, D Pisharoty, U Raghuram, O Karlsson, ...
US Patent App. 14/793,005, 2015
52015
Distributed substrate top contact for moscap measurements
S Mujumdar, A Joshi
US Patent App. 13/544,710, 2014
32014
Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices
AS Lee, P Besser, K Choi, EL Haywood, H Kim, S Mujumdar
US Patent 9,607,904, 2017
22017
Semiconductor Device Metal-Insulator-Semiconductor Contacts with Interface Layers and Methods for Forming the Same
A Joshi, S Barstow, P Besser, A Bodke, G Bouche, N Fuchigami, Z Hong, ...
US Patent App. 14/576,597, 2016
22016
Gate structures for transistor devices for CMOS applications and products
Z Hong, S Tzeng, A Joshi, A Bodke, D Pisharoty, U Raghuram, O Karlsson, ...
US Patent 9,362,283, 2016
22016
Sacrificial Low Work Function Cap Layer
S Mujumdar, A Joshi
US Patent App. 13/645,259, 2014
22014
Impact of thermal treatments on the schottky barrier height reduction at the Ti-TiOx-Si interface for contact resistance reduction
A Lee, A Pethe, A Joshi, G Bouche, S Koh, H Nimii, S Mujumdar, Z Hong, ...
2014 Silicon Nanoelectronics Workshop (SNW), 1-2, 2014
12014
Strain engineering for strained p-channel Non-planar Tri-Gate field effect transistors
SS Mujumdar
12011
Combining Materials in Different Components of Selector Elements of Integrated Circuits
S Mujumdar, A Pethe, A Bodke, K Kashefi
US Patent App. 15/235,992, 2017
2017
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Articles 1–20