Kris Gaj
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Very compact FPGA implementation of the AES algorithm
P Chodowiec, K Gaj
International workshop on cryptographic hardware and embedded systems, 319-333, 2003
An embedded true random number generator for FPGAs
P Kohlbrenner, K Gaj
Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004
Comparison of the hardware performance of the AES candidates using reconfigurable hardware
K Gaj, P Chodowiec
The promise of high-performance reconfigurable computing
T El-Ghazawi, E El-Araby, M Huang, K Gaj, V Kindratenko, D Buell
Computer 41 (2), 69-76, 2008
Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays
K Gaj, P Chodowiec
Cryptographers’ Track at the RSA Conference, 84-99, 2001
Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs
K Gaj, E Homsirikamol, M Rogawski
International Workshop on Cryptographic Hardware and Embedded Systems, 264-278, 2010
FPGA and ASIC implementations of AES
K Gaj, P Chodowiec
Cryptographic engineering, 235-294, 2009
Timing of multi-gigahertz rapid single flux quantum digital circuits
K Gaj, EG Friedman, MJ Feldman
Journal of VLSI signal processing systems for signal, image and video …, 1997
New hardware architectures for Montgomery modular multiplication algorithm
M Huang, K Gaj, T El-Ghazawi
IEEE Transactions on computers 60 (7), 923-936, 2010
Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512
T Grembowski, R Lien, K Gaj, N Nguyen, P Bellows, J Flidr, T Lehman, ...
Information Security: 5th International Conference, ISC 2002 Sao Paulo …, 2002
Fast implementations of secret-key block ciphers using mixed inner-and outer-round pipelining
P Chodowiec, P Khuon, K Gaj
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field …, 2001
Lut-lock: A novel lut-based logic obfuscation for fpga-bitstream and asic-hardware protection
HM Kamali, KZ Azar, K Gaj, H Homayoun, A Sasan
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 405-410, 2018
A configurable ring-oscillator-based PUF for Xilinx FPGAs
X Xin, JP Kaps, K Gaj
2011 14th Euromicro conference on digital system design, 651-657, 2011
ATHENa-automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs
K Gaj, JP Kaps, V Amirineni, M Rogawski, E Homsirikamol, BY Brewster
2010 International Conference on Field Programmable Logic and Applications …, 2010
Guest editors' introduction: high-performance reconfigurable computing
D Buell, T El-Ghazawi, K Gaj, V Kindratenko
Computer 40 (03), 23-27, 2007
Tools for the computer-aided design of multigigahertz superconducting digital circuits
K Gaj, QP Herr, V Adler, A Krasniewski, EG Friedman, MJ Feldman
IEEE transactions on applied superconductivity 9 (1), 18-38, 1999
Comprehensive evaluation of high-speed and medium-speed implementations of five SHA-3 finalists using Xilinx and Altera FPGAs
K Gaj, E Homsirikamol, M Rogawski, R Shahid, MU Sharif
Cryptology ePrint Archive, 2012
A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512
R Lien, T Grembowski, K Gaj
Topics in Cryptology–CT-RSA 2004: The Cryptographers’ Track at the RSA …, 2004
Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates
D Hwang, M Chaney, S Karanam, N Ton, K Gaj
The State of the Art of Stream Ciphers, 151-162, 2008
Implementation and benchmarking of round 2 candidates in the NIST post-quantum cryptography standardization process using hardware and software/hardware co-design approaches
VB Dang, F Farahmand, M Andrzejczak, K Mohajerani, DT Nguyen, K Gaj
Cryptology ePrint Archive: Report 2020/795, 2020
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