| 7.7 LNPU: A 25.3 TFLOPS/W sparse deep-neural-network learning processor with fine-grained mixed precision of FP8-FP16 J Lee, J Lee, D Han, J Lee, G Park, HJ Yoo 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 142-144, 2019 | 158 | 2019 |
| A low-power convolutional neural network face recognition processor and a CIS integrated with always-on face detector K Bong, S Choi, C Kim, D Han, HJ Yoo IEEE Journal of Solid-State Circuits 53 (1), 115-123, 2017 | 104 | 2017 |
| 7.4 GANPU: A 135TFLOPS/W multi-DNN training processor for GANs with speculative dual-sparsity exploitation S Kang, D Han, J Lee, D Im, S Kim, S Kim, HJ Yoo 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 140-142, 2020 | 61 | 2020 |
| HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching D Han, HJ Yoo On-Chip Training NPU-Algorithm, Architecture and SoC Design, 121-161, 2023 | 51 | 2023 |
| A low-power deep neural network online learning processor for real-time object tracking application D Han, J Lee, J Lee, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 66 (5), 1794-1804, 2018 | 50 | 2018 |
| DT-CNN: Dilated and transposed convolution neural network accelerator for real-time image segmentation on mobile devices D Im, D Han, S Choi, S Kang, HJ Yoo 2019 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2019 | 47 | 2019 |
| A 1.32 TOPS/W energy efficient deep neural network learning processor with direct feedback alignment based heterogeneous core architecture D Han, J Lee, J Lee, HJ Yoo 2019 Symposium on VLSI Circuits, C304-C305, 2019 | 42 | 2019 |
| The hardware and algorithm co-design for energy-efficient DNN processor on edge/mobile devices J Lee, S Kang, J Lee, D Shin, D Han, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (10), 3458-3470, 2020 | 39 | 2020 |
| DT-CNN: An energy-efficient dilated and transposed convolutional neural network processor for region of interest based image segmentation D Im, D Han, S Choi, S Kang, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (10), 3471-3483, 2020 | 34 | 2020 |
| GANPU: An energy-efficient multi-DNN training processor for GANs with speculative dual-sparsity exploitation S Kang, D Han, J Lee, D Im, S Kim, S Kim, J Ryu, HJ Yoo IEEE Journal of Solid-State Circuits 56 (9), 2845-2857, 2021 | 29 | 2021 |
| A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices D Han, J Lee, J Lee, S Choi, HJ Yoo 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018 | 21* | 2018 |
| DF-LNPU: A Pipelined Direct Feedback Alignment Based Deep Neural Network Learning Processor for Fast Online Learning D Han, HJ Yoo On-Chip Training NPU-Algorithm, Architecture and SoC Design, 95-119, 2023 | 18 | 2023 |
| An energy-efficient sparse deep-neural-network learning accelerator with fine-grained mixed precision of FP8–FP16 J Lee, J Lee, D Han, J Lee, G Park, HJ Yoo IEEE Solid-State Circuits Letters 2 (11), 232-235, 2019 | 18 | 2019 |
| A 36.2 dB high SNR and PVT/leakage-robust eDRAM computing-in-memory macro with segmented BL and reference cell array S Ha, S Kim, D Han, S Um, HJ Yoo IEEE Transactions on Circuits and Systems II: Express Briefs 69 (5), 2433-2437, 2022 | 17 | 2022 |
| A 1.02-μW STT-MRAM-Based DNN ECG Arrhythmia Monitoring SoC With Leakage-Based Delay MAC Unit KR Lee, J Kim, C Kim, D Han, J Lee, J Lee, H Jeong, HJ Yoo IEEE Solid-State Circuits Letters 3, 390-393, 2020 | 16 | 2020 |
| Efficient convolutional neural network training with direct feedback alignment D Han, H Yoo arXiv preprint arXiv:1901.01986, 2019 | 15 | 2019 |
| An overview of sparsity exploitation in CNNs for on-device intelligence with software-hardware cross-layer optimizations S Kang, G Park, S Kim, S Kim, D Han, HJ Yoo IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11 (4 …, 2021 | 14 | 2021 |
| A 1.15 TOPS/W energy-efficient capsule network accelerator for real-time 3D point cloud segmentation in mobile environment G Park, D Im, D Han, HJ Yoo IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1594-1598, 2020 | 13 | 2020 |
| A 4.45 ms low-latency 3D point-cloud-based neural network processor for hand pose estimation in immersive wearable devices D Im, S Kang, D Han, S Choi, HJ Yoo 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 13 | 2020 |
| OmniDRL: A 29.3 TFLOPS/W deep reinforcement learning processor with dualmode weight compression and on-chip sparse weight transposer J Lee, S Kim, S Kim, W Jo, D Han, J Lee, HJ Yoo 2021 Symposium on VLSI Circuits, 1-2, 2021 | 12 | 2021 |
Dongseok ImKorea Advanced Institute of Science and Technology (KAIST)kaist.ac.kr의 이메일 확인됨
