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Dan Ernst
Dan Ernst
Verified email at microsoft.com
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Cited by
Cited by
Year
MiBench: A free, commercially representative embedded benchmark suite
MR Guthaus, JS Ringenberg, D Ernst, TM Austin, T Mudge, RB Brown
Proceedings of the fourth annual IEEE international workshop on workload …, 2001
48482001
SimpleScalar: An infrastructure for computer system modeling
T Austin, E Larson, D Ernst
Computer 35 (2), 59-67, 2002
23332002
Razor: A low-power pipeline based on circuit-level timing speculation
D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ...
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
17732003
Razor: circuit-level correction of timing errors for low-power operation
D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner
IEEE Micro 24 (6), 10-20, 2004
5392004
Efficient dynamic scheduling through tag elimination
D Ernst, T Austin
ACM SIGARCH Computer Architecture News 30 (2), 37-46, 2002
1412002
Pond: Cxl-based memory pooling systems for cloud platforms
H Li, DS Berger, L Hsu, D Ernst, P Zardoshti, S Novakovic, M Shah, ...
Proceedings of the 28th ACM International Conference on Architectural …, 2023
1152023
Cyclone: A broadcast-free dynamic instruction scheduler with selective replay
D Ernst, A Hamel, T Austin
ACM SIGARCH Computer Architecture News 31 (2), 253-263, 2003
1122003
Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and Trevor Mudge. Razor: A low-power pipeline based on …
D Ernst, NS Kim
and Ann Arbor, 2003
962003
Concurrent CS: preparing students for a multicore world
DJ Ernst, DE Stevenson
13th annual conference on Innovation and technology in computer science …, 2008
512008
First-generation memory disaggregation for cloud platforms
H Li, DS Berger, S Novakovic, L Hsu, D Ernst, P Zardoshti, M Shah, ...
arXiv preprint arXiv:2203.00241, 2022
392022
Shidhartha Das, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Nam Sung Kim, and Krisztián Flautner. Razor: circuit-level correction of timing errors for low-power operation
D Ernst
IEEE Micro 24 (6), 10-20, 2004
292004
Performance analysis using pipeline visualization.
CT Weaver, KC Barr, ED Marsman, D Ernst, TM Austin
ISPASS, 18-21, 2001
202001
Design tradeoffs in cxl-based memory pools for public cloud platforms
DS Berger, D Ernst, H Li, P Zardoshti, M Shah, S Rajadnya, S Lee, L Hsu, ...
IEEE Micro 43 (2), 30-38, 2023
122023
Hybrid and custom data structures: evolution of the data structures course
DJ Ernst, DE Stevenson, PJ Wagner
Proceedings of the 14th annual ACM SIGCSE conference on Innovation and …, 2009
122009
A New Methodological Approach to the Characterization of Optimal Charging Rates at the Hydrogen Plasma Smelting Reduction Process Part 1: Method
MA Zarl, D Ernst, J Cejka, J Schenk
Materials 15 (14), 4767, 2022
102022
Preparing students for future architectures with an exploration of multi-and many-core performance
DJ Ernst
Proceedings of the 16th annual joint conference on Innovation and technology …, 2011
102011
A New Methodological Approach on the Characterization of Optimal Charging Rates at the Hydrogen Plasma Smelting Reduction Process Part 2: Results
D Ernst, MA Zarl, J Cejka, J Schenk
Materials 15 (12), 4065, 2022
82022
Preparing students for ubiquitous parallelism
D Ernst, B Wittman, B Harvey, T Murphy, M Wrinn
Proceedings of the 40th ACM technical symposium on Computer science …, 2009
82009
Technique for reduced-tag dynamic scheduling and reduced-tag prediction
DJ Ernst, TM Austin
US Patent 7,398,375, 2008
72008
Shidhartha Das, Sanjay Pant, Toan Pham, Rajeev Rao, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge, and Krisztián Flautner. Razor: A Low-Power Pipeline Based on …
D Ernst, NS Kim
Proc. 36th Intl. Symp. Microarch, 7-18, 2003
72003
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