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Kunal Banerjee
Kunal Banerjee
Data Science Foundation, Walmart
walmartlabs.com의 이메일 확인됨 - 홈페이지
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A study of BFLOAT16 for deep learning training
D Kalamkar, D Mudigere, N Mellempudi, D Das, K Banerjee, S Avancha, ...
arXiv preprint arXiv:1905.12322, 2019
3202019
Mixed precision training of convolutional neural networks using integer operations
D Das, N Mellempudi, D Mudigere, D Kalamkar, S Avancha, K Banerjee, ...
International Conference on Learning Representations (ICLR), 2018
1912018
Anatomy of high-performance deep learning convolutions on simd architectures
E Georganas, S Avancha, K Banerjee, D Kalamkar, G Henry, H Pabst, ...
SC18: International Conference for High Performance Computing, Networking …, 2018
1272018
Verification of code motion techniques using value propagation
K Banerjee, C Karfa, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
702014
Exploring Alternatives to Softmax Function
K Banerjee, V Prasad C, RR Gupta, K Vyas, A H, B Mishra
https://arxiv.org/abs/2011.11538, 2020
542020
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviours
C Karfa, K Banerjee, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
312013
Reliability evaluation of compressed deep learning models
BF Goldstein, S Srinivasan, D Das, K Banerjee, L Santiago, VC Ferreira, ...
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-5, 2020
292020
Harnessing deep learning via a single building block
E Georganas, K Banerjee, D Kalamkar, S Avancha, A Venkat, ...
2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2020
232020
Extending the FSMD framework for validating code motions of array-handling programs
K Banerjee, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
172014
Ternary Residual Networks
A Kundu, K Banerjee, N Mellempudi, D Mudigere, D Das, B Kaul, ...
SysML, 2018
152018
Ternary Residual Networks
A Kundu, K Banerjee, N Mellempudi, D Mudigere, D Das, B Kaul, ...
https://arxiv.org/abs/1707.04679, 2017
152017
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
S Bandyopadhyay, K Banerjee, D Sarkar, C Mandal
Progress in VLSI Design and Test (VDAT), 69-78, 2012
152012
A path construction algorithm for translation validation using PRES+ models
S Bandyopadhyay, D Sarkar, C Mandal, K Banerjee, KR Duddu
Parallel Processing Letters 26 (02), 1650010, 2016
142016
Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers
K Banerjee, C Mandal, D Sarkar
IMPECS-POPL Workshop on Emerging Research and Development Trends in …, 2015
14*2015
A study of BFLOAT16 for deep learning training (2019)
D Kalamkar, D Mudigere, N Mellempudi, D Das, K Banerjee, S Avancha, ...
arXiv preprint arXiv:1905.12322, 1905
141905
Automated Checking of the Violation of Precedence of Conditions in else-if Constructs in Students' Programs
KK Sharma, K Banerjee, I Vikas, C Mandal
International Conference on MOOC, Innovation and Technology in Education …, 2014
132014
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques
K Banerjee, C Karfa, D Sarkar, C Mandal
International Symposium on Electronic System Design (ISED), 67-71, 2012
132012
A Path-based Equivalence Checking Method for Petri Net based Models of Programs
S Bandyopadhyay, D Sarkar, K Banerjee, C Mandal
International Conference on Software Engineering and Applications (ICSOFT-EA …, 2015
122015
Optimizing deep learning rnn topologies on intel architecture
K Banerjee, E Georganas, DD Kalamkar, B Ziv, E Segal, C Anderson, ...
Supercomputing Frontiers and Innovations 6 (3), 64-85, 2019
112019
High-performance deep learning via a single building block
E Georganas, K Banerjee, D Kalamkar, S Avancha, A Venkat, ...
arXiv preprint arXiv:1906.06440, 2019
112019
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