A study of BFLOAT16 for deep learning training D Kalamkar, D Mudigere, N Mellempudi, D Das, K Banerjee, S Avancha, ... arXiv preprint arXiv:1905.12322, 2019 | 342 | 2019 |
Mixed precision training of convolutional neural networks using integer operations D Das, N Mellempudi, D Mudigere, D Kalamkar, S Avancha, K Banerjee, ... International Conference on Learning Representations (ICLR), 2018 | 201 | 2018 |
Anatomy of high-performance deep learning convolutions on simd architectures E Georganas, S Avancha, K Banerjee, D Kalamkar, G Henry, H Pabst, ... SC18: International Conference for High Performance Computing, Networking …, 2018 | 138 | 2018 |
Verification of code motion techniques using value propagation K Banerjee, C Karfa, D Sarkar, C Mandal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 72 | 2014 |
Exploring Alternatives to Softmax Function K Banerjee, V Prasad C, RR Gupta, K Vyas, A H, B Mishra https://arxiv.org/abs/2011.11538, 2020 | 60 | 2020 |
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviours C Karfa, K Banerjee, D Sarkar, C Mandal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 31 | 2013 |
Reliability evaluation of compressed deep learning models BF Goldstein, S Srinivasan, D Das, K Banerjee, L Santiago, VC Ferreira, ... 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-5, 2020 | 29 | 2020 |
Harnessing deep learning via a single building block E Georganas, K Banerjee, D Kalamkar, S Avancha, A Venkat, ... 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2020 | 25 | 2020 |
Extending the FSMD framework for validating code motions of array-handling programs K Banerjee, D Sarkar, C Mandal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 19 | 2014 |
Ternary Residual Networks A Kundu, K Banerjee, N Mellempudi, D Mudigere, D Das, B Kaul, ... SysML, 2018 | 15 | 2018 |
Ternary Residual Networks A Kundu, K Banerjee, N Mellempudi, D Mudigere, D Das, B Kaul, ... https://arxiv.org/abs/1707.04679, 2017 | 15 | 2017 |
Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers K Banerjee, C Mandal, D Sarkar IMPECS-POPL Workshop on Emerging Research and Development Trends in …, 2015 | 15* | 2015 |
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker S Bandyopadhyay, K Banerjee, D Sarkar, C Mandal Progress in VLSI Design and Test (VDAT), 69-78, 2012 | 15 | 2012 |
A study of BFLOAT16 for deep learning training (2019) D Kalamkar, D Mudigere, N Mellempudi, D Das, K Banerjee, S Avancha, ... arXiv preprint arXiv:1905.12322, 1905 | 15 | 1905 |
A path construction algorithm for translation validation using PRES+ models S Bandyopadhyay, D Sarkar, C Mandal, K Banerjee, KR Duddu Parallel Processing Letters 26 (02), 1650010, 2016 | 14 | 2016 |
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques K Banerjee, C Karfa, D Sarkar, C Mandal International Symposium on Electronic System Design (ISED), 67-71, 2012 | 14 | 2012 |
A Path-based Equivalence Checking Method for Petri Net based Models of Programs S Bandyopadhyay, D Sarkar, K Banerjee, C Mandal International Conference on Software Engineering and Applications (ICSOFT-EA …, 2015 | 13 | 2015 |
Automated Checking of the Violation of Precedence of Conditions in else-if Constructs in Students' Programs KK Sharma, K Banerjee, I Vikas, C Mandal International Conference on MOOC, Innovation and Technology in Education …, 2014 | 13 | 2014 |
Optimizing deep learning rnn topologies on intel architecture K Banerjee, E Georganas, DD Kalamkar, B Ziv, E Segal, C Anderson, ... Supercomputing Frontiers and Innovations 6 (3), 64-85, 2019 | 11 | 2019 |
High-performance deep learning via a single building block E Georganas, K Banerjee, D Kalamkar, S Avancha, A Venkat, ... arXiv preprint arXiv:1906.06440, 2019 | 11 | 2019 |