Yipeng Wang
Yipeng Wang
Intel Labs
intel.com의 이메일 확인됨
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Obfusmem: A low-overhead access obfuscation for trusted memories
A Awad, Y Wang, D Shands, Y Solihin
Proceedings of the 44th Annual International Symposium on Computer …, 2017
602017
CAF: Core to core communication acceleration framework
Y Wang, R Wang, A Herdrich, J Tsai, Y Solihin
2016 International Conference on Parallel Architecture and Compilation …, 2016
192016
Metoo: Stochastic modeling of memory traffic timing behavior
Y Wang, G Balakrishnan, Y Solihin
2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015
112015
HALO: accelerating flow classification for scalable packet processing in NFV
Y Yuan, Y Wang, R Wang, J Huang
2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture …, 2019
92019
Optimizing open vswitch to support millions of flows
Y Wang, TYC Tai, R Wang, S Gobriel, J Tseng, J Tsai
GLOBECOM 2017-2017 IEEE Global Communications Conference, 1-7, 2017
92017
Flow classification apparatus, methods, and systems
R Wang, TYC Tai, Y Wang, S Gobriel
US Patent App. 15/638,102, 2018
82018
Accelerating open vSwitch with integrated GPU
J Tseng, R Wang, J Tsai, Y Wang, TYC Tai
Proceedings of the Workshop on Kernel-Bypass Networks, 7-12, 2017
82017
Systems and methods for modeling memory access behavior and memory traffic timing behavior
Y Solihin, Y Wang, A Awad
US Patent 9,846,627, 2017
72017
Methods and apparatus to facilitate field-programmable gate array support during runtime execution of computer readable instructions
X Guo, S Dutta, H Lee, Y Wang
US Patent 10,445,118, 2019
42019
Multi-core communication acceleration using hardware queue device
R Wang, NN Venkatesan, D Bernstein, E Verplanke, SR Van Doren, ...
US Patent 10,445,271, 2019
42019
Emulating cache organizations on real hardware using performance cloning
Y Wang, Y Solihin
2015 IEEE International Symposium on Performance Analysis of Systems and …, 2015
42015
Hash table design and optimization for software virtual switches
Y Wang, S Gobriel, R Wang, TYC Tai, C Dumitrescu
Proceedings of the 2018 Afternoon Workshop on Kernel Bypassing Networks, 22-28, 2018
32018
Processors, methods, and systems to allocate load and store buffers based on instruction type
AJ Herdrich, Y Wang, R Wang, TYC Tai, JS Tsai
US Patent App. 15/089,533, 2017
32017
Accurate cloning of the memory access behavior
A Awad, G Balakrishnan, Y Wang, Y Solihin
IPSJ Transactions on System LSI Design Methodology 9, 49-60, 2016
32016
Technologies for classifying network flows using adaptive virtual routing
Y Wang, R Wang, J Tseng, JS Tsai, TY Tai
US Patent App. 15/999,133, 2019
22019
Offload of data lookup operations
R Wang, AJ Herdrich, TYC Tai, Y Wang, R Kondapalli, A Bachmutsky, ...
US Patent App. 16/207,065, 2019
12019
Techniques to control an insertion ratio for a cache
Y Wang, R Wang, S Gobriel, TYC Tai
US Patent 10,845,995, 2020
2020
Technologies for a least recently used cache replacement policy using vector instructions
R Wang, Y Wang, TY Tai, CF Dumitrescu, X Guo
US Patent 10,789,176, 2020
2020
Dynamic Sketch: Efficient and Adjustable Heavy Hitter Detection for Software Packet Processing
Y Wang, T Yang, R Wang, C Tai
2019 IEEE 8th International Conference on Cloud Networking (CloudNet), 1-7, 2019
2019
Technologies for flow rule aware exact match cache compression
Y Wang, R Wang, A Fischetti, S Gobriel, TYC Tai
US Patent App. 15/862,311, 2019
2019
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