| Building trusted ICs using split fabrication K Vaidyanathan, BP Das, E Sumbul, R Liu, L Pileggi 2014 IEEE international symposium on hardware-oriented security and trust …, 2014 | 129 | 2014 |
| Within-die gate delay variability measurement using reconfigurable ring oscillator BP Das, B Amrutur, HS Jamadagni, NV Arvind, V Visvanathan IEEE Transactions on Semiconductor Manufacturing 22 (2), 256-267, 2009 | 73 | 2009 |
| Detecting reliability attacks during split fabrication using test-only BEOL stack K Vaidyanathan, BP Das, L Pileggi Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 49 | 2014 |
| Warning prediction sequential for transient error prevention BP Das, H Onodera 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI …, 2010 | 22 | 2010 |
| Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs BP Das, H Onodera Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 22 (12), 2013 | 18 | 2013 |
| On-chip measurement of rise/fall gate delay using reconfigurable ring oscillator BP Das, H Onodera IEEE Transactions on Circuits and Systems II: Express Briefs 61 (3), 183-187, 2014 | 17 | 2014 |
| Gate delay measurement circuit and method of determining a delay of a logic gate B Amrutur, BP Das US Patent 8,224,604, 2012 | 15 | 2012 |
| Voltage and temperature-aware SSTA using neural network delay model BP Das, B Amrutur, HS Jamadagni, NV Arvind, V Visvanathan IEEE transactions on semiconductor manufacturing 24 (4), 533-544, 2011 | 14 | 2011 |
| Low overhead warning flip-flop based on charge sharing for timing slack monitoring G Sannena, BP Das IEEE transactions on very large scale integration (VLSI) systems 26 (7 …, 2018 | 13 | 2018 |
| Voltage and temperature scalable gate delay and slew models including intra-gate variations BP Das, V Janakiraman, B Amrutur, HS Jamadagni, NV Arvind 21st International Conference on VLSI Design (VLSID 2008), 685-691, 2008 | 11 | 2008 |
| On-chip threshold voltage variability estimation using reconfigurable ring oscillator P Jain, BP Das IEEE Transactions on Semiconductor Manufacturing 32 (2), 226-235, 2019 | 10 | 2019 |
| Voltage and temperature scalable standard cell leakage models based on stacks for statistical leakage characterization J Viraraghavan, BP Das, B Amrutur 21st International Conference on VLSI Design (VLSID 2008), 667-672, 2008 | 10 | 2008 |
| Metastability immune and area efficient error masking flip-flop for timing error resilient designs G Sannena, BP Das Integration 61, 101-113, 2018 | 7 | 2018 |
| A metastability immune timing error masking flip-flop for dynamic variation tolerance G Sannena, BP Das Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 151-156, 2016 | 7 | 2016 |
| Random Local Delay Variability: On-chip Measurement And Modeling BP Das | 7 | 2011 |
| Area-efficient reconfigurable-array-based oscillator for standard cell characterisation BP Das, H Onodera IET Circuits, Devices & Systems 6 (6), 429-436, 2012 | 6 | 2012 |
| Design and analysis of leakage-induced false error tolerant error detecting latch for sub/near-threshold applications P Sharma, BP Das IEEE Transactions on Device and Materials Reliability 20 (2), 366-375, 2020 | 5 | 2020 |
| An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications P Sharma, P Jain, BP Das Microelectronics Journal 92, 104613, 2019 | 5 | 2019 |
| In-memory computation with improved linearity using adaptive sparsity-based compact thermometric code PK Saragada, BP Das IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (10 …, 2022 | 4 | 2022 |
| Low latency scaling-free pipeline CORDIC architecture using augmented Taylor series SS Wadkar, BP Das, PK Meher 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | 4 | 2019 |
Bharadwaj AmruturIndian Institute of Scienceiisc.ac.in의 이메일 확인됨
