| Area-efficient and variation-tolerant in-memory BNN computing using 6T SRAM array J Kim, J Koo, T Kim, Y Kim, H Kim, S Yoo, JJ Kim 2019 Symposium on VLSI Circuits, C118-C119, 2019 | 79 | 2019 |
| Integrate circuit content addressable memories JT Koo Lehigh University, 1969 | 37 | 1969 |
| A 16K dynamic RAM C Ahlquist, J Breivogel, J Koo, J McCollum, W Oldham, A Renninger 1976 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1976 | 31 | 1976 |
| Efficient synapse memory structure for reconfigurable digital neuromorphic hardware J Kim, J Koo, T Kim, JJ Kim Frontiers in neuroscience 12, 416978, 2018 | 24 | 2018 |
| A 44.1 TOPS/W precision-scalable accelerator for quantized neural networks in 28nm CMOS S Ryu, H Kim, W Yi, J Koo, E Kim, Y Kim, T Kim, JJ Kim 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020 | 12 | 2020 |
| Power distribution network simulation method using variable reduction method JE Koo, KH Lee, YH Cheon US Patent 7,509,596, 2009 | 10 | 2009 |
| Configurable BCAM/TCAM based on 6T SRAM bit cell and enhanced match line clamping J Koo, E Kim, S Yoo, T Kim, S Ryu, JJ Kim 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 223-226, 2019 | 8 | 2019 |
| Area-efficient transposable 6T SRAM for fast online learning in neuromorphic processors J Koo, J Kim, S Ryu, C Kim, JJ Kim 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 7 | 2019 |
| Variation-tolerant elastic clock scheme for low-voltage operations S Ryu, J Koo, W Kim, Y Kim, JJ Kim IEEE Journal of Solid-State Circuits 56 (7), 2245-2255, 2021 | 5 | 2021 |
| Sampson Ron JH Zhang, R Venigalla, DC Stoll, J Wallner, JF Thompson, J Sun, ... Proc. VMIC 25, 95, 2008 | 5 | 2008 |
| Area-efficient transposable crossbar synapse memory using 6T SRAM bit cell for fast online learning of neuromorphic processors J Koo, J Kim, S Ryu, C Kim, JJ Kim JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 20 (2), 195-203, 2020 | 3 | 2020 |
| Simulating electronic circuits including charge pumps S Sarkar, JE Koo US Patent 10,289,778, 2019 | 3 | 2019 |
| Method of operating simulator compensating for delay and device for performing the same JE Koo, YJ Gu, IY Lee US Patent 9,727,674, 2017 | 3 | 2017 |
| Low design overhead timing error correction scheme for elastic clock methodology S Ryu, J Koo, JJ Kim 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 3 | 2017 |
| Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines J Koo, E Song, E Park, D Kim, J Park, S Ryu, S Yoo, JJ Kim 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 137-140, 2016 | 3 | 2016 |
| Fast power delivery network analyzer B Hwang, J Koo, C Hwang, Y Cheon, S Ahn, J Lee, M Yoo 2011 12th International Symposium on Quality Electronic Design, 1-4, 2011 | 2 | 2011 |
| Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines J Koo, E Park, D Kim, J Park, S Ryu, S Yoo, JJ Kim IEICE Electronics Express 16 (11), 20190180-20190180, 2019 | 1 | 2019 |
| A variable reduction technique for the analysis of ultra large-scale power distribution networks JE Koo, KH Lee, YH Cheon, JH Choi, MH Yoo, JT Kong International Symposium on Signals, Circuits and Systems. Proceedings, SCS …, 2004 | 1 | 2004 |
| Thermal analysis of high level radiowaste repository using a large model JH Park, JE Koo, CH Kang | 1 | 1999 |
| Modeling system, method of modeling semiconductor device, computer-readable recording medium comprising program for performing the method GU Young-Jin, JE Koo, KS Lee US Patent 9,223,927, 2015 | | 2015 |
