Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration W Maly, N Singh, Z Chen, N Shen, X Li, A Pfitzner, D Kasprowicz, ... Proceedings of the 18th International Conference Mixed Design of Integrated …, 2011 | 78 | 2011 |
Ionization of impurities in silicon W Kuzmicz Solid-state electronics 29 (12), 1223-1227, 1986 | 67 | 1986 |
CMOS standard cells characterization for defect based testing WA Pleskacz, D Kasprowicz, T Oleszczak, W Kuzmicz Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance …, 2001 | 46 | 2001 |
Fuzzy logic controller for rate-adaptive heart pacemaker A Wojtasik, Z Jaworski, W Kuźmicz, A Wielgus, A Wałkanis, D Sarna Applied Soft Computing 4 (3), 259-270, 2004 | 32 | 2004 |
Defect-oriented fault simulation and test generation in digital circuits W Kuzmicz, W Pleskacz, J Raik, R Ubar Proceedings of the IEEE 2001. 2nd International Symposium on Quality …, 2001 | 32 | 2001 |
Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation Z Jaworski, M Niewczas, W Kuzmicz Proceedings. 15th IEEE VLSI Test Symposium (Cat. No. 97TB100125), 172-176, 1997 | 30 | 1997 |
Coupling a statistical process-device simulator with a circuit layout extractor for a realistic circuit simulation of VLSI circuits W Kuźmicz, W Denisiuk, J Gempel, Z Jaworski, M Niewczas, A Pfitzner, ... Simulation of Semiconductor Devices and Processes: Vol. 5, 37-40, 1993 | 29 | 1993 |
Hierarchical defect-oriented fault simulation for digital circuits M Blyzniuk, T Cibakova, E Gramatova, W Kuzmicz, M Lobur, W Pleskacz, ... Proceedings IEEE European Test Workshop, 69-74, 2000 | 27 | 2000 |
Fuzzy logic-based diagnostic algorithm for implantable cardioverter defibrillators A Bárdossy, A Blinowska, W Kuzmicz, J Ollitrault, M Lewandowski, ... Artificial intelligence in medicine 60 (2), 113-121, 2014 | 22 | 2014 |
Static power consumption in nano-cmos circuits: Physics and modelling W Kuzmicz, E Piwowarska, A Pfitzner, D Kasprowicz 2007 14th International Conference on Mixed Design of Integrated Circuits …, 2007 | 22 | 2007 |
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement M Blyzniuk, I Kazymyra, W Kuzmicz, WA Pleskacz, J Raik, R Ubar Microelectronics Reliability 41 (12), 2023-2040, 2001 | 19 | 2001 |
Hierarchical test generation for combinational circuits with real defects coverage T Cibakova, M Fischerová, E Gramatova, W Kuzmicz, WA Pleskacz, ... Microelectronics Reliability 42 (7), 1141-1149, 2002 | 17 | 2002 |
DOT: New deterministic defect-oriented ATPG tool J Raik, R Ubar, J Sudbrock, W Kuzmicz, W Pleskacz European Test Symposium (ETS'05), 96-101, 2005 | 16 | 2005 |
Resistive Plate Chamber (RPC) based muon trigger system for the CMS experiment–pattern comparator ASIC Z Jaworski, IM Kudla, W Kuzmicz, M Niewczas Nuclear Instruments and Methods in Physics Research Section A: Accelerators …, 1998 | 15 | 1998 |
Statistical many-dimensional simulation of VLSI technology based on response surface methodology MV Kazitov, WB Kuzmicz, VV Nelayev, VR Stempitsky Third International Workshop on Nondestructive Testing and Computer …, 2000 | 14 | 2000 |
Heavy doping parameters estimated from transistor measurements W Kuzmicz, W Zagozdzon-Wosik Solid-state electronics 31 (5), 911-919, 1988 | 13 | 1988 |
Defect-oriented library builder and hierarchical test generation T Cibakova, E Gramatova, W Kuźmicz, W Pleskacz, J Raik, R Ubar IEEE 4th International Symposium on Design and Diagnostics of Electonic …, 2001 | 12 | 2001 |
Defect oriented fault coverage of 100% stuck-at fault test sets M Blyzniuk, T Cibakova, E Gramatova, W Kuźmicz, M Lobur, W Pleskacz, ... 7th International Conference Mixed Design of Integrated Circuits and Systems, 2000 | 12 | 2000 |
Estimation of probability of different functional faults caused by spot defects in VLSI circuits M Blyzniuk, W Pleskacz, M Lobur, W Kuzmicz Proc. International Conference on Modern Problems of Telecommunications …, 1999 | 12 | 1999 |
Defect-oriented test-and layout-generation for standard-cell ASIC designs J Sudbrock, J Raik, R Ubar, W Kuzmicz, W Pleskacz Digital System Design, 2005. Proceedings. 8th Euromicro Conference on, 79-82, 2005 | 11 | 2005 |