| Interconnect limits on gigascale integration (GSI) in the 21st century JA Davis, R Venkatesan, A Kaloyeros, M Beylansky, SJ Souri, K Banerjee, ... Proceedings of the IEEE 89 (3), 305-324, 2001 | 927 | 2001 |
| Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing HS Yang, R Malik, S Narasimha, Y Li, R Divakaruni, P Agnello, S Allen, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 234 | 2004 |
| Structure and method to improve channel mobility by gate electrode stress modification MP Belyansky, D Chidambarrao, OH Dokumaci, BB Doris, O Gluschenkov US Patent 6,977,194, 2005 | 218 | 2005 |
| High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography P Agnello, T Ivers, C Warm, R Wise, R Wachnik, D Schepis, S Sankaran, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 133 | 2006 |
| Stressed semiconductor device structures having granular semiconductor material BB Doris, MP Belyansky, DC Boyd, D Chidambarrao, O Gluschenkov US Patent 7,122,849, 2006 | 104 | 2006 |
| Method of fabricating mobility enhanced CMOS devices MP Belyansky, BB Doris, O Gluschenkov US Patent 7,205,206, 2007 | 100 | 2007 |
| Structure and method to improve channel mobility by gate electrode stress modification MP Belyansky, D Chidambarrao, OH Dokumaci, BB Doris, O Gluschenkov US Patent 7,750,410, 2010 | 92 | 2010 |
| Structure and method to improve channel mobility by gate electrode stress modification M Belyansky, D Chidambarrao, O Dokumaci, B Doris, O Gluschenkov US Patent App. 11/201,163, 2005 | 90 | 2005 |
| High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E Leobandung, H Nayakama, D Mocuta, K Miyamoto, M Angyal, HV Meer, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 126-127, 2005 | 85 | 2005 |
| A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-all-Around NanoSheet Devices M Nicolas Loubet, Subhadeep Kal, Cheryl Alix, Shanti Pancharatnam, Huimei ... International Electron Devices Meeting (IEDM), 2019 | 68* | 2019 |
| Method of producing highly strained PECVD silicon nitride thin films at low temperature MP Belyansky, O Gluschenkov, Y Li, A Mallikarjunan US Patent 7,585,704, 2009 | 60 | 2009 |
| High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper B Greene, Q Liang, K Amarnath, Y Wang, J Schaeffer, M Cai, Y Liang, ... 2009 Symposium on VLSI Technology, 140-141, 2009 | 60 | 2009 |
| Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress TA Brunner, VC Menon, CW Wong, O Gluschenkov, MP Belyansky, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 12 (4), 043002-043002, 2013 | 55 | 2013 |
| Methods of producing plasma enhanced chemical vapor deposition silicon nitride thin films with high compressive and tensile stress M Belyansky, M Chace, O Gluschenkov, J Kempisty, N Klymko, A Madan, ... Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 26 (3 …, 2008 | 54 | 2008 |
| High density plasma oxidation M Belyansky, O Glushenkov, A Knorr US Patent 7,273,638, 2007 | 53 | 2007 |
| Trench isolation employing a doped oxide trench fill M Belyansky, A Knorr, O Gluschenkov, C Parks US Patent 6,890,833, 2005 | 50 | 2005 |
| Oxidation method for altering a film structure and CMOS transistor structure formed therewith MP Belyansky, DC Boyd, BB Doris, O Gluschenkov US Patent 6,982,196, 2006 | 44 | 2006 |
| Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond C Davis, JH Ku, T Schiml, J Sudijono, I Yang, A Steegen, D Coolbough, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 60-61, 2006 | 42 | 2006 |
| Boron Chemical Shifts in B6O M Belyansky, M Trenary, C Ellison Surface science spectra 3 (2), 147-150, 1994 | 34 | 1994 |
| High performance bulk planar 20nm CMOS technology for low power mobile applications H Shang, S Jain, E Josse, E Alptekin, MH Nam, SW Kim, KH Cho, I Kim, ... 2012 Symposium on VLSI Technology (VLSIT), 129-130, 2012 | 30 | 2012 |
