| VLSI implementation of deep neural network using integral stochastic computing A Ardakani, F Leduc-Primeau, N Onizawa, T Hanyu, WJ Gross IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017 | 287 | 2017 |
| An architecture to accelerate convolution in deep neural networks A Ardakani, C Condo, M Ahmadi, WJ Gross IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1349-1362, 2017 | 128 | 2017 |
| Sparsely-connected neural networks: towards efficient VLSI implementation of deep neural networks A Ardakani, C Condo, WJ Gross International Conference on Learning Representations (ICLR) 2017, 2017 | 107 | 2017 |
| Fast and efficient convolutional accelerator for edge computing A Ardakani, C Condo, WJ Gross IEEE Transactions on Computers 69 (1), 138-152, 2019 | 50 | 2019 |
| Stochastic computing can improve upon digital spiking neural networks SC Smithson, K Boga, A Ardakani, BH Meyer, WJ Gross 2016 IEEE International Workshop on Signal Processing Systems (SiPS), 309-314, 2016 | 43 | 2016 |
| Design and implementation of a polar codes blind detection scheme C Condo, SA Hashemi, A Ardakani, F Ercan, WJ Gross IEEE Transactions on Circuits and Systems II: Express Briefs 66 (6), 943-947, 2018 | 34 | 2018 |
| Learning Recurrent Binary/Ternary Weights A Ardakani, Z Ji, SC Smithson, BH Meyer, WJ Gross International Conference on Learning Representations (ICLR) 2019, 2019 | 33 | 2019 |
| Hardware implementation of FIR/IIR digital filters using integral stochastic computation A Ardakani, F Leduc-Primeau, WJ Gross 2016 IEEE International Conference on Acoustics, Speech and Signal …, 2016 | 24 | 2016 |
| A convolutional accelerator for neural networks with binary weights A Ardakani, C Condo, WJ Gross 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 19 | 2018 |
| A novel area-efficient VLSI architecture for recursion computation in LTE turbo decoders A Ardakani, M Shabany IEEE Transactions on Circuits and Systems II: Express Briefs 62 (6), 568-572, 2015 | 17 | 2015 |
| Learning to Skip Ineffectual Recurrent Computations in LSTMs A Ardakani, Z Ji, WJ Gross Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, 2019 | 16 | 2019 |
| An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding A Ardakani, M Mahdavi, M Shabany 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 797-800, 2013 | 16 | 2013 |
| The vital role of pistachio processing industries in development of Iran non-oil exports ASH Ardakani IV International Symposium on Pistachios and Almonds 726, 579-582, 2005 | 15 | 2005 |
| Optimizing of the process of pistachio butter production AS Ardakani, M Shahedi, G Kabir IV International Symposium on Pistachios and Almonds 726, 565-568, 2005 | 15 | 2005 |
| The synthesis of XNOR recurrent neural networks with stochastic logic A Ardakani, Z Ji, A Ardakani, W Gross Advances in Neural Information Processing Systems 32, 2019 | 14 | 2019 |
| Activation pruning of deep convolutional neural networks A Ardakani, C Condo, WJ Gross 2017 IEEE Global Conference on Signal and Information Processing (GlobalSIP …, 2017 | 13 | 2017 |
| Optimizing formulation of pistachio butter production. AS Ardakani, M Shahedi, G Kabir | 10 | 2009 |
| An efficient max-log map algorithm for vlsi implementation of turbo decoders A Ardakani, M Shabany 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1794-1797, 2015 | 9 | 2015 |
| Hardware-aware design for edge intelligence WJ Gross, BH Meyer, A Ardakani IEEE Open Journal of Circuits and Systems 2, 113-127, 2020 | 7 | 2020 |
| Training linear finite-state machines A Ardakani, A Ardakani, W Gross Advances in Neural Information Processing Systems 33, 7173-7183, 2020 | 6 | 2020 |
Warren GrossProfessor of Electrical and Computer Engineering, McGill UniversityVerified email at mcgill.ca
