| Space vector based hybrid PWM techniques for reduced current ripple G Narayanan, D Zhao, HK Krishnamurthy, R Ayyanar, VT Ranganathan IEEE Transactions on Industrial Electronics 55 (4), 1614-1627, 2008 | 379 | 2008 |
| Optimal variable switching frequency scheme for reducing switching loss in single-phase inverters based on time-domain ripple analysis X Mao, R Ayyanar, HK Krishnamurthy IEEE Transactions on Power Electronics 24 (4), 991-1001, 2009 | 208 | 2009 |
| Advanced bus-clamping PWM techniques based on space vector approach G Narayanan, HK Krishnamurthy, D Zhao, R Ayyanar IEEE Transactions on Power Electronics 21 (4), 974-984, 2006 | 206* | 2006 |
| Reduction of torque ripple in induction motor drives using an advanced hybrid PWM technique K Basu, JSS Prasad, G Narayanan, HK Krishnamurthy, R Ayyanar IEEE Transactions on Industrial Electronics 57 (6), 2085-2091, 2009 | 145 | 2009 |
| Building block converter module for universal (ac-dc, dc-ac, dc-dc) fully modular power conversion architecture HK Krishnamurthy, R Ayyanar 2007 IEEE Power Electronics Specialists Conference, 483-489, 2007 | 119 | 2007 |
| A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14-nm tri-gate CMOS HK Krishnamurthy, V Vaidya, P Kumar, R Jain, S Weng, ST Kim, ... IEEE Journal of Solid-State Circuits 53 (1), 8-19, 2017 | 100 | 2017 |
| A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS HK Krishnamurthy, VA Vaidya, P Kumar, GE Matthew, S Weng, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 81 | 2014 |
| Vertical stacked LEGO-PoL CPU voltage regulator J Baek, Y Elasser, K Radhakrishnan, H Gan, JP Douglas, ... IEEE Transactions on Power Electronics 37 (6), 6305-6322, 2021 | 62 | 2021 |
| Stability analysis of cascaded converters for bidirectional power flow applications H Krishnamurthy, R Ayyanar INTELEC 2008-2008 IEEE 30th International Telecommunications Energy …, 2008 | 50 | 2008 |
| 27.3 EM and power SCA-resilient AES-256 in 65nm cmos through> 350× current-domain signature attenuation D Das, J Danial, A Golder, N Modak, S Maity, B Chatterjee, D Seo, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 424-426, 2020 | 43 | 2020 |
| EM and power SCA-resilient AES-256 through> 350× current-domain signature attenuation and local lower metal routing D Das, J Danial, A Golder, N Modak, S Maity, B Chatterjee, DH Seo, ... IEEE Journal of Solid-State Circuits 56 (1), 136-150, 2020 | 40 | 2020 |
| Multiple voltage identification (VID) power architecture, a digital synthesizable low dropout regulator, and apparatus for improving reliability of power gates R Muthukaruppan, HK Krishnamurthy, M Verma, P Patra, UB Kadali US Patent 9,766,678, 2017 | 40 | 2017 |
| A variation-adaptive integrated computational digital LDO in 22-nm CMOS with fast transient response KZ Ahmed, HK Krishnamurthy, C Augustine, X Liu, S Weng, ... IEEE Journal of Solid-State Circuits 55 (4), 977-987, 2020 | 39 | 2020 |
| 14.7 A modular hybrid LDO with fast load-transient response and programmable PSRR in 14nm CMOS featuring dynamic clamp tuning and time-constant compensation X Liu, HK Krishnamurthy, T Na, S Weng, KZ Ahmed, K Ravichandran, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2019 | 39 | 2019 |
| A digitally controlled fully integrated voltage regulator with 3-D-TSV-based on-die solenoid inductor with a planar magnetic core for 3-D-stacked die applications in 14-nm tri … HK Krishnamurthy, S Weng, GE Mathew, N Desai, R Saraswat, ... IEEE journal of solid-state circuits 53 (4), 1038-1048, 2017 | 39 | 2017 |
| Design of space vector-based hybrid PWM techniques for reduced current ripple H Krishnamurthy, G Narayanan, R Ayyanar, VT Ranganathan Eighteenth Annual IEEE Applied Power Electronics Conference and Exposition …, 2003 | 38 | 2003 |
| A 0.4V∼1V 0.2A/mm270% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri … P Kumar, VA Vaidya, H Krishnamurthy, S Kim, GE Matthew, S Weng, ... 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 35 | 2015 |
| 8.5 A fully integrated voltage regulator in 14nm CMOS with package-embedded air-core inductor featuring self-trimmed, digitally controlled variable on-time discontinuous … C Schaef, N Desai, H Krishnamurthy, S Weng, H Do, W Lambert, ... 2019 IEEE international solid-state circuits conference-(ISSCC), 154-156, 2019 | 28 | 2019 |
| A digitally controlled linear regulator for per-core wide-range DVFS of atom™ cores in 14nm tri-gate CMOS featuring non-linear control, adaptive gain and code roaming R Muthukaruppan, T Mahajan, HK Krishnamurthy, S Mangal, ... ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 275-278, 2017 | 27 | 2017 |
| Selectable-mode voltage regulator topology P Kumar, HK Krishnamurthy US Patent App. 14/582,956, 2016 | 27 | 2016 |
