| Architecture, chip, and package co-design flow for 2.5 D IC design enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, V Chaitanya, K Chekuri, N Dasari, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 49 | 2019 |
| Architecture, chip, and package codesign flow for interposer-based 2.5-D chiplet integration enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, VCK Chekuri, NM Rahman, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (11 …, 2020 | 47 | 2020 |
| A spectral convolutional net for co-optimization of integrated voltage regulators and embedded inductors HM Torun, H Yu, N Dasari, VCK Chekuri, A Singh, J Kim, SK Lim, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 21 | 2019 |
| Automatic GDSII generator for on-chip voltage regulator for easy integration in digital SoCs VCK Chekuri, N Dasari, A Singh, S Mukhopadhyay 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 5 | 2019 |
| On the effect of NBTI induced aging of power stage on the transient performance of on-chip voltage regulators VCK Chekuri, A Singh, N Dasari, S Mukhopadhyay 2019 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2019 | 4 | 2019 |
| Modeling of Integrated Voltage Regulator Power delivery systems N Dasari Georgia Institute of Technology, 2020 | | 2020 |
