| Nanotechnology Based Sensitive Biosesors For Covid-19 Prediction using Fuzzy Logic Control V Maheshwari Journal of NanoMaterials 2021, 2021 | 32 | 2021 |
| Area optimization of CMOS full adder design using 3T XOR S Malipatil, V Maheshwari, MB Chandra 2020 International conference on wireless communications signal processing …, 2020 | 21 | 2020 |
| Brain tumor detection by microwave imaging using planner antenna H Gupta, V Maheshwari, VV Thakery International Journal of Bio-science and Bio-technology 8 (5), 201-210, 2016 | 13 | 2016 |
| An explicit crosstalk aware delay modelling for on-chip VLSI RLC interconnect with skin effect V Maheshwari, S Lavania, D Sengupta, R Kar, D Mandal, ... Journal of Electron Devices 10, 499-505, 2011 | 13 | 2011 |
| Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90nm process technology A Gupta, V Maheshwari, S Sharma, R Kar International Conference on Computing, Communication & Automation, 1215-1219, 2015 | 10 | 2015 |
| A review on image processing A Kour, VK Yadav, V Maheshwari, D Prashar International Journal of Electronics Communication and Computer Engineering …, 2013 | 10 | 2013 |
| Delay analysis for on-chip VLSI interconnect using gamma distribution function R Kar, V Maheshwari, AK Mal, AK Bhattacharjee International Journal of Computer Application 1 (3), 65-68, 2010 | 10 | 2010 |
| Fault tolerant reversible full adder design using gate diffusion input S Malipatil, A Gour, V Maheshwari 2020 International Conference on Smart Technologies in Computing, Electrical …, 2020 | 8 | 2020 |
| Efficient coupled noise estimation for RLC on-chip interconnect V Maheshwari, S Gupta, K Khare, V Yadav, R Kar, D Mandal, ... 2012 IEEE Symposium on Humanities, Science and Engineering Research, 1125-1129, 2012 | 7 | 2012 |
| An explicit approach for delay evaluation for on-chip RC interconnects using beta distribution function by moment matching technique R Kar, V Maheshwari, S Pathak, MSK Reddy, AK Mal, AK Bhattacharjee 2010 International Conference on Recent Trends in Information …, 2010 | 7 | 2010 |
| Modeling of on-chip global RLCG interconnect delay for step input R Kar, V Maheshwari, A Choudhary, A Singh 2010 International Conference on Computer and Communication Technology …, 2010 | 6 | 2010 |
| Coupling aware explicit delay metric for on-chip rlc interconnect for ramp input R Kar, V Maheshwari, A Choudhary, A Singh International Journal of Signal & Image Processing (IJSIP) 1 (2), 14-19, 2010 | 6 | 2010 |
| Design & implementation of reconfigurable adaptive fault tolerant system for ALU S Malipatil, A Gour, V Maheshwari International Journal of Electrical Engineering and Technology 11 (9), 01-07, 2020 | 5 | 2020 |
| Delay model for VLSI RLCG global interconnects line V Maheshwari, A Baboo, B Kumar, R Kar, D Mandal, AK Bhattacharjee 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics …, 2012 | 5 | 2012 |
| Moment based delay modelling for on-chip RC global VLSI interconnect for unit ramp input A Halder, V Maheshwari, A Goyal, R Kar, D Mandal, AK Bhattacharjee 2012 Ninth International Conference on Computer Science and Software …, 2012 | 5 | 2012 |
| Accurate estimation of on-chip global RLC interconnect delay for step input R Kar, V Maheshwari, V Agarwal, A Choudhary, A Singh, AK Mai, ... 2010 International Conference on Computer and Communication Technology …, 2010 | 5 | 2010 |
| Crosstalk aware bandwidth modeling for distributed on-chip RLCG interconnects using difference model approach R Kar, V Maheshwari, M Maqbool, S Mondal, AK Mal, AK Bhattacharjee 2010 Second International conference on Computing, Communication and …, 2010 | 5 | 2010 |
| Closed Form Expressions for Delay to Ramp Inputs for On-Chip VLSI RC Interconnect V Maheshwari, P Sharma, A Goyal, VK Yadav, S Kumar National Conference on Emerging Trends in Electrical, Instrumentation …, 0 | 5 | |
| An accurate crosstalk noise estimation method for two simultaneously switched on-chip VLSI distributed RLCG global interconnects R Kar, V Maheshwari, A Choudhary, A Singh, AK Mal, AK Bhattacharjee 2010 International Conference on Signal and Image Processing, 362-367, 2010 | 4 | 2010 |
| An accurate delay metric for global on-chip vlsi rc interconnects using first three circuit moments R Kar, V Maheshwari, MSK Reddy, V Agarwal, AK Mal, AK Bhattacharjee 14th VLSI Design And Test Symposium (VDAT 2010), July, 7-9, 2010 | 4 | 2010 |
Rajib KarAssociate Professor, Department of ECE, NIT Durgapur, IndiaVerified email at nitdgp.ac.in
