| Drisa: A dram-based reconfigurable in-situ accelerator S Li, D Niu, KT Malladi, H Zheng, B Brennan, Y Xie Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 369 | 2017 |
| Towards energy-proportional datacenter memory with mobile DRAM KT Malladi, BC Lee, FA Nothaft, C Kozyrakis, K Periyathambi, M Horowitz ACM SIGARCH Computer Architecture News 40 (3), 37-48, 2012 | 344 | 2012 |
| LazyPIM: An efficient cache coherence mechanism for processing-in-memory A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, K Hsieh, KT Malladi, ... IEEE Computer Architecture Letters 16 (1), 46-50, 2016 | 200 | 2016 |
| CoNDA: Efficient cache coherence support for near-data accelerators A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, R Ausavarungnirun, ... Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 108 | 2019 |
| Scope: A stochastic computing engine for dram-based in-situ accelerator S Li, AO Glova, X Hu, P Gu, D Niu, KT Malladi, H Zheng, B Brennan, Y Xie 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 94 | 2018 |
| Rethinking DRAM power modes for energy proportionality KT Malladi, I Shaeffer, L Gopalakrishnan, D Lo, BC Lee, M Horowitz 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 131-142, 2012 | 91 | 2012 |
| Reconfigurable logic architecture M Gao, H Zheng, KT Malladi, R Brennan US Patent 9,577,644, 2017 | 43 | 2017 |
| DPU architecture S Li, D Niu, K Malladi, H Zheng US Patent 10,242,728, 2019 | 35 | 2019 |
| DRAF: A low-power DRAM-based reconfigurable acceleration fabric M Gao, C Delimitrou, D Niu, KT Malladi, H Zheng, B Brennan, C Kozyrakis ACM SIGARCH Computer Architecture News 44 (3), 506-518, 2016 | 35 | 2016 |
| Performance analysis of containerized applications on local and remote storage Q Xu, M Awasthi, KT Malladi, J Bhimani, J Yang, M Annavaram, M Hsieh Proc. of MSST 3, 24-28, 2017 | 34 | 2017 |
| Multi-tier buffer management and storage system design for non-volatile memory J Arulraj, A Pavlo, KT Malladi arXiv preprint arXiv:1901.10938, 2019 | 33 | 2019 |
| DLUX: A LUT-based near-bank accelerator for data center deep learning training workloads P Gu, X Xie, S Li, D Niu, H Zheng, KT Malladi, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 27 | 2020 |
| Electronic system with partitioning mechanism and method of operation thereof D Niu, H Zheng, K Malladi US Patent 9,727,239, 2017 | 24 | 2017 |
| LazyPIM: Efficient support for cache coherence in processing-in-memory architectures A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, N Hajinazar, ... arXiv preprint arXiv:1706.03162, 2017 | 20 | 2017 |
| FlexDrive: A framework to explore NVMe storage solutions KT Malladi, M Awasthi, H Zheng 2016 IEEE 18th International Conference on High Performance Computing and …, 2016 | 17 | 2016 |
| Nest: Dimm based near-data-processing accelerator for k-mer counting W Huangfu, KT Malladi, S Li, P Gu, Y Xie Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 16 | 2020 |
| Docker characterization on high performance SSDs Q Xu, M Awasthi, KT Malladi, J Bhimani, J Yang, M Annavaram 2017 IEEE International Symposium on Performance Analysis of Systems and …, 2017 | 16 | 2017 |
| Enabling CXL memory expansion for in-memory database management systems M Ahn, A Chang, D Lee, J Gim, J Kim, J Jung, O Rebholz, V Pham, ... Proceedings of the 18th International Workshop on Data Management on New …, 2022 | 15 | 2022 |
| Rack-level scheduling for reducing the long tail latency using high performance SSDS Q Xu, K Malladi, M Awasthi US Patent 10,628,233, 2020 | 15 | 2020 |
| Memory apparatus for in-chip error correction KT Malladi, H Zheng US Patent 10,379,939, 2019 | 14 | 2019 |
Dimin NiuComputing Technology Lab, Alibaba DAMO AcademyVerified email at alibaba-inc.com
