Manjunath Shevgoor
Manjunath Shevgoor
Microprocessor Architect, Apple
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Cited by
Cited by
Usimm: the utah simulated memory module
N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ...
University of Utah, Tech. Rep, 1-24, 2012
Efficiently Prefetching Complex Address Patterns
M Shevgoor, S Koladiya, R Balasubramonian, S Pugsley, C Wilkerson, ...
IEEE/ACM International Symposium on Microarchitecture 48, 2015
Efficient scrub mechanisms for error-prone emerging memories
M Awasthi, M Shevgoor, K Sudan, B Rajendran, R Balasubramonian, ...
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
Leveraging heterogeneity in DRAM main memories to accelerate critical word access
N Chatterjee, M Shevgoor, R Balasubramonian, A Davis, Z Fang, R Illikkal, ...
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 13-24, 2012
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
M Shevgoor, JS Kim, N Chatterjee, R Balasubramonian, A Davis, ...
Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013
Avoiding information leakage in the memory controller with fixed service policies
A Shafiee, A Gundu, M Shevgoor, R Balasubramonian, M Tiwari
Proceedings of the 48th International Symposium on Microarchitecture, 89-101, 2015
Improving memristor memory with sneak current sharing
M Shevgoor, N Muralimanohar, R Balasubramonian, Y Jeon
2015 33rd IEEE International conference on computer design (ICCD), 549-556, 2015
A case for near data security
A Gundu, AS Ardestani, M Shevgoor, R Balasubramonian
Workshop on Near-Data Processing, 2014
Handling PCM resistance drift with device, circuit, architecture, and system solutions
M Awasthi, M Shevgoor, K Sudan, R Balasubramonian, B Rajendran, ...
Non-Volatile Memories Workshop, 2011
Method and system for coordinating baseline and secondary prefetchers
SH Pugsley, M Shevgoor, CB Wilkerson
US Patent 10,678,692, 2020
N Chatterjee, R Balasubramonian, M Shevgoor, SH Pugsley, AN Udipi, ...
University of Utah, 2012
Inter-cluster communication of live-in register values
S Pediaditaki, E Schuchman, RBR Chowdhury, M Shevgoor
US Patent 10,437,590, 2019
Apparatus and method for an early page predictor for a memory paging subsystem
M Dechene, M Shevgoor, F Guvenilir, Z Zhang, J Perry
US Patent 10,860,319, 2020
Technology For Providing Memory Atomicity With Low Overhead
M Shevgoor, MJ Dechene, V Mekkat, JM Agron, Z Zhang
US Patent App. 16/367,409, 2020
System, method, and apparatus for enhanced pointer identification and prefetching
S Subramoney, S Shwartsman, A Nori, S Balachandran, E Shtiegmann, ...
US Patent 11,080,194, 2021
Addressing service interruptions in memory with thread-to-rank assignment
M Shevgoor, R Balasubramonian, N Chatterjee, JS Kim
2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016
Enabling big memory with emerging technologies
M Shevgoor
The University of Utah, 2016
Designing a fast and reliable main memory with memristor technology
M Shevgoor, N Muralimanohar, R Balasubramonian
Hardware processor having multiple memory prefetchers and multiple prefetch filters
S Pugsley, M Dechene, R Carlson, M Shevgoor
US Patent App. 17/958,334, 2024
System, method, and apparatus for enhanced pointer identification and prefetching
S Subramoney, S Shwartsman, A Nori, S Balachandran, E Shtiegmann, ...
US Patent App. 18/320,780, 2023
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