| Instruction set compiled simulation: A technique for fast and flexible instruction set simulation M Reshadi, P Mishra, N Dutt Proceedings of the 40th Annual Design Automation Conference, 758-763, 2003 | 198 | 2003 |
| LOSSLESS DATA COMPRESSION AND REAL-TIME DECOMPRESSION P Mishra, SW Seong, K Basu, W Wang, X Qin, C Murthy US Patent App. 12/682,808, 2008 | 192 | 2008 |
| Processor description languages: applications and methodologies P Mishra, N Dutt Morgan Kaufmann, 2008 | 165* | 2008 |
| A survey of side-channel attacks on caches and countermeasures Y Lyu, P Mishra Journal of Hardware and Systems Security 2, 33-50, 2018 | 156 | 2018 |
| Functional coverage driven test generation for validation of pipelined processors P Mishra, N Dutt Design, Automation and Test in Europe, 2005. Proceedings, 678-683 Vol. 2, 2005 | 150* | 2005 |
| MERS: statistical test generation for side-channel analysis based Trojan detection Y Huang, S Bhunia, P Mishra Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications …, 2016 | 127 | 2016 |
| Hardware IP security and trust P Mishra, S Bhunia, M Tehranipoor Springer International Publishing, 2017 | 120 | 2017 |
| Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems W Wang, P Mishra, S Ranka Proceedings of the 48th Design Automation Conference, 948-953, 2011 | 119 | 2011 |
| Scalable test generation for Trojan detection using side channel analysis Y Huang, S Bhunia, P Mishra IEEE Transactions on Information Forensics and Security 13 (11), 2746-2760, 2018 | 118 | 2018 |
| Architecture description languages for programmable embedded systems P Mishra, N Dutt Computers and Digital Techniques, IEE Proceedings- 152 (3), 285-297, 2005 | 115 | 2005 |
| Real-time detection and localization of distributed DoS attacks in NoC-based SoCs S Charles, Y Lyu, P Mishra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 99 | 2020 |
| Pre-silicon security verification and validation: A formal perspective X Guo, RG Dutta, Y Jin, F Farahmandi, P Mishra Proceedings of the 52nd annual design automation conference, 1-6, 2015 | 98 | 2015 |
| Bitmask-based code compression for embedded systems SW Seong, P Mishra IEEE Transactions on computer-aided design of integrated circuits and …, 2008 | 97 | 2008 |
| RATS: Restoration-aware trace signal selection for post-silicon validation K Basu, P Mishra IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (4), 605-613, 2012 | 96 | 2012 |
| Automated test generation for hardware trojan detection using reinforcement learning Z Pan, P Mishra Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 93 | 2021 |
| An automated configurable Trojan insertion framework for dynamic trust benchmarks J Cruz, Y Huang, P Mishra, S Bhunia 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 90 | 2018 |
| Graph-based functional test program generation for pipelined processors P Mishra, N Dutt Design, Automation and Test in Europe Conference and Exhibition, 2004 …, 2004 | 90 | 2004 |
| Hardware Trojan detection using ATPG and model checking J Cruz, F Farahmandi, A Ahmed, P Mishra 2018 31st international conference on VLSI design and 2018 17th …, 2018 | 87 | 2018 |
| Test data compression using efficient bitmask and dictionary selection methods K Basu, P Mishra IEEE transactions on very large scale integration (VLSI) systems 18 (9 …, 2009 | 84 | 2009 |
| Post-silicon validation in the SoC era: A tutorial introduction P Mishra, R Morad, A Ziv, S Ray IEEE Design & Test 34 (3), 68-92, 2017 | 82 | 2017 |
Nikil DuttDistinguished Professor, CS, EECS & Cognitive Sciences, University of California, Irvineuci.edu의 이메일 확인됨
