| 29.1 A 40nm 64Kb 56.67 TOPS/W read-disturb-tolerant compute-in-memory/digital RRAM macro with active-feedback-based read and in-situ write verification JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 404-406, 2021 | 70 | 2021 |
| 27.3 EM and power SCA-resilient AES-256 in 65nm cmos through> 350ื current-domain signature attenuation D Das, J Danial, A Golder, N Modak, S Maity, B Chatterjee, D Seo, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 424-426, 2020 | 43 | 2020 |
| EM and power SCA-resilient AES-256 through> 350ื current-domain signature attenuation and local lower metal routing D Das, J Danial, A Golder, N Modak, S Maity, B Chatterjee, DH Seo, ... IEEE Journal of Solid-State Circuits 56 (1), 136-150, 2020 | 40 | 2020 |
| A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range SD Spetalnick, M Chang, B Crafton, WS Khwa, YD Chih, MF Chang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 38 | 2022 |
| A 40-nm, 64-Kb, 56.67 TOPS/W voltage-sensing computing-in-memory/digital RRAM macro supporting iterative write with verification and online read-disturb detection JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury IEEE Journal of Solid-State Circuits 57 (1), 68-79, 2021 | 32 | 2021 |
| A 40nm 60.64 TOPS/W ECC-capable compute-in-memory/digital 2.25 MB/768KB RRAM/SRAM system with embedded cortex M3 microprocessor for edge recommendation systems M Chang, SD Spetalnick, B Crafton, WS Khwa, YD Chih, MF Chang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 31 | 2022 |
| A 40-nm 118.44-TOPS/W voltage-sensing compute-in-memory RRAM macro with write verification and multi-bit encoding JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury IEEE Journal of Solid-State Circuits 57 (3), 845-857, 2022 | 28 | 2022 |
| 14.1 a 65nm 1.1-to-9.1 tops/w hybrid-digital-mixed-signal computing platform for accelerating model-based and model-free swarm robotics N Cao, M Chang, A Raychowdhury 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 222-224, 2019 | 27 | 2019 |
| A 65nm image processing SoC supporting multiple DNN models and real-time computation-communication trade-off via actor-critical neuro-controller N Cao, B Chatterjee, M Gong, M Chang, S Sen, A Raychowdhury 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 21 | 2020 |
| A 40nm 100Kb 118.44 TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 15 | 2021 |
| A 65-nm 8-to-3-b 1.0–0.36-V 9.1–1.1-TOPS/W hybrid-digital-mixed-signal computing platform for accelerating swarm robotics N Cao, M Chang, A Raychowdhury IEEE Journal of Solid-State Circuits 55 (1), 49-59, 2019 | 14 | 2019 |
| A 73.53 TOPS/W 14.74 TOPS heterogeneous RRAM in-memory and SRAM near-memory SoC for hybrid frame and event-based target tracking M Chang, AS Lele, SD Spetalnick, B Crafton, S Konno, Z Wan, A Bhat, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 426-428, 2023 | 13 | 2023 |
| A 65nm thermometer-encoded time/charge-based compute-in-memory neural network accelerator at 0.735 pJ/MAC and 0.41 pJ/Update M Gong, N Cao, M Chang, A Raychowdhury IEEE Transactions on Circuits and Systems II: Express Briefs 68 (4), 1408-1412, 2020 | 13 | 2020 |
| An analog clock-free compute fabric base on continuous-time dynamical system for solving combinatorial optimization problems M Chang, X Yin, Z Toroczkai, X Hu, A Raychowdhury 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 9 | 2022 |
| A FerroFET-based in-memory processor for solving distributed and iterative optimizations via least-squares method I Yoon, M Chang, K Ni, M Jerry, S Gangopadhyay, GH Smith, T Hamam, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5 …, 2019 | 9 | 2019 |
| A FeFET based processing-in-memory architecture for solving distributed least-square optimizations I Yoon, M Chang, K Ni, M Jerry, S Gangopadhyay, G Smith, T Hamam, ... 2018 76th Device Research Conference (DRC), 1-2, 2018 | 8 | 2018 |
| 27.3 EM and power SCA-r AES-256 in 65nm CMOS through> 350◦ current-domain signature attenuation. In 2020 IEEE International Solid-State Circuits Conference (ISSCC). 424–426 D Das, J Danial, A Golder, N Modak, S Maity, B Chatterjee, D Seo, ... | 6 | 2020 |
| A 65 nm wireless image SoC supporting on-chip DNN optimization and real-time computation-communication trade-off via actor-critical neuro-controller N Cao, B Chatterjee, J Liu, B Cheng, M Gong, M Chang, S Sen, ... IEEE Journal of Solid-State Circuits 57 (8), 2545-2559, 2022 | 5 | 2022 |
| A heterogeneous rram in-memory and sram near-memory soc for fused frame and event-based target identification and tracking AS Lele, M Chang, SD Spetalnick, B Crafton, S Konno, Z Wan, A Bhat, ... IEEE Journal of Solid-State Circuits, 2023 | 4 | 2023 |
| A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation SD Spetalnick, M Chang, S Konno, B Crafton, AS Lele, WS Khwa, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 4 | 2023 |
Arijit RaychowdhurySteve W. Chaddick School Chair for ECE, Georgia Institute of TechnologyVerified email at ece.gatech.edu
