Dae-gyu Park
Dae-gyu Park
Senior Manager, IBM T.J.Watson Research Center
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Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys
B Hekmatshoar-Tabari, M Hopstaken, DG Park, DK Sadana, GG Shahidi, ...
US Patent 8,778,448, 2014
2112014
Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys
B Hekmatshoar-Tabari, M Hopstaken, DG Park, DK Sadana, GG Shahidi, ...
US Patent 9,099,585, 2015
2102015
METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES
AJ Kellock, H Kim, DG Park, SV Nitta, S Purushothaman, S Rossnagel, ...
US Patent App. 12/203,338, 2010
2072010
Sharp reduction of contact resistivities by effective Schottky barrier lowering with silicides as diffusion sources
Z Zhang, F Pagette, C D'emic, B Yang, C Lavoie, Y Zhu, M Hopstaken, ...
IEEE Electron Device Letters 31 (7), 731-733, 2010
2002010
Method of forming a metal gate in a semiconductor device using atomic layer deposition process
2007 DG Park, HJ Cho, KY Lim - US Patent 7,157,359
US Patent 20,020,086,507, 0
189*
High-/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length
MH Khater, Z Zhang, J Cai, C Lavoie, C D'Emic, Q Yang, B Yang, ...
IEEE Electron Device Letters 31 (4), 275-277, 2010
1592010
Robust diffusion barrier for Cu-interconnect technology with subnanometer thickness by metal-organic plasma-enhanced atomic layer deposition
H Kim, C Detavenier, O Van der Straten, SM Rossnagel, AJ Kellock, ...
Journal of applied physics 98 (1), 014308, 2005
1432005
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ...
2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011
1132011
Method of manufacturing semiconductor devices with titanium aluminum nitride work function
DG Park, TH Cha, SA Jang, HJ Cho, TK Kim, KY Lim, IS Yeo, JW Park
US Patent 6,506,676, 2003
1112003
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ...
2007 IEEE Symposium on VLSI Technology, 194-195, 2007
1082007
Characteristics of n+ polycrystalline-Si/Al 2 O 3/Si metal–oxide–semiconductor structures prepared by atomic layer chemical vapor deposition using Al (CH 3) 3 and H 2 O vapor
DG Park, HJ Cho, KY Lim, C Lim, IS Yeo, JS Roh, JW Park
Journal of Applied Physics 89 (11), 6275-6280, 2001
962001
finFETS and methods of making same
KK Chan, TS Kanarsky, J Li, CQ Ouyang, DG Park, Z Ren, X Wang, H Yin
US Patent 8,043,920, 2011
912011
FinFET with longitudinal stress in a channel
KK Chan, QC Ouyang, DG Park, X Wang
US Patent 7,872,303, 2011
822011
Electrical conduction in silicon nitrides deposited by plasma enhanced chemical vapour deposition
M Tao, D Park, SN Mohammad, D Li, AE Botchkerav, H Morkoç
Philosophical Magazine B 73 (4), 723-736, 1996
821996
Gate quality Si3N4 prepared by low temperature remote plasma enhanced chemical vapor deposition for III–V semiconductor‐based metal–insulator …
DG Park, M Tao, D Li, AE Botchkarev, Z Fan, Z Wang, SN Mohammad, ...
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 1996
751996
High-temperature stable gate structure with metallic electrode
DG Park, OG Gluschenkov, MA Gribelyuk, KH Wong
US Patent 7,279,413, 2007
722007
Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs
H Miki, N Tega, M Yamaoka, DJ Frank, A Bansal, M Kobayashi, K Cheng, ...
2012 International Electron Devices Meeting, 19.1. 1-19.1. 4, 2012
682012
The physical properties of cubic plasma-enhanced atomic layer deposition TaN films
H Kim, C Lavoie, M Copel, V Narayanan, DG Park, SM Rossnagel
Journal of applied physics 95 (10), 5848-5855, 2004
672004
Boron penetration in metal–oxide–semiconductor system
DG Park, HJ Cho, IS Yeo, JS Roh, JM Hwang
Applied Physics Letters 77 (14), 2207-2209, 2000
672000
Thermally robust dual-work function ALD-MN/sub x/MOSFETs using conventional CMOS process flow
DG Park, ZJ Luo, N Edleman, W Zhu, P Nguyen, K Wong, C Cabral, ...
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 186-187, 2004
612004
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