| Flexible circuits and architectures for ultralow power BH Calhoun, JF Ryan, S Khanna, M Putic, J Lach Proceedings of the IEEE 98 (2), 267-282, 2010 | 153 | 2010 |
| An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep … SC Bartling, S Khanna, MP Clinton, SR Summerfelt, JA Rodriguez, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 88 | 2013 |
| Sub-threshold circuit design with shrinking CMOS devices BH Calhoun, S Khanna, R Mann, J Wang 2009 IEEE International Symposium on Circuits and Systems, 2541-2544, 2009 | 87 | 2009 |
| An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at 0 V Achieving Zero Leakage With 400-ns Wakeup Time for ULP … S Khanna, SC Bartling, M Clinton, S Summerfelt, JA Rodriguez, ... IEEE Journal of Solid-State Circuits 49 (1), 95-106, 2013 | 83 | 2013 |
| Impact of circuit assist methods on margin and performance in 6T SRAM RW Mann, J Wang, S Nalam, S Khanna, G Braceras, H Pilo, BH Calhoun Solid-State Electronics 54 (11), 1398-1407, 2010 | 75 | 2010 |
| A 1.2 µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83–92% efficiency across wide input and output voltages A Shrivastava, YK Ramadass, S Khanna, S Bartling, BH Calhoun 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 43 | 2014 |
| A 32 b 90 nm processor implementing panoptic DVS achieving energy efficient operation from sub-threshold to high performance K Craig, Y Shakhsheer, S Arrabi, S Khanna, J Lach, BH Calhoun IEEE Journal of Solid-State Circuits 49 (2), 545-552, 2013 | 39 | 2013 |
| System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms BH Calhoun, S Khanna, Y Zhang, J Ryan, B Otis Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 34 | 2010 |
| Priority based backup in nonvolatile logic arrays SC Bartling, S Khanna US Patent 9,899,066, 2018 | 30 | 2018 |
| A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25 V to 1.2 V Y Shakhsheer, S Khanna, K Craig, S Arrabi, J Lach, BH Calhoun 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 23 | 2011 |
| Customizable backup and restore from nonvolatile logic array SC Bartling, S Khanna US Patent 9,335,954, 2016 | 22 | 2016 |
| Signal level conversion in nonvolatile bitcell array SC Bartling, S Khanna US Patent 8,854,858, 2014 | 22 | 2014 |
| Nonvolatile logic array with built-in test drivers SC Bartling, S Khanna US Patent 8,792,288, 2014 | 21 | 2014 |
| Nonvolatile logic array with retention flip flops to reduce switching power during wakeup SC Bartling, S Khanna US Patent 9,058,126, 2015 | 17 | 2015 |
| Nonvolatile backup of a machine state when a power supply drops below a threshhold SC Bartling, S Khanna US Patent 9,715,911, 2017 | 16 | 2017 |
| Serial sub-threshold circuits for ultra-low-power systems S Khanna, BH Calhoun Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009 | 14 | 2009 |
| Sub-threshold operation and cross-hierarchy design for ultra low power wearable sensors BH Calhoun, J Bolus, S Khanna, AD Jurik, AC Weaver, TN Blalock 2009 IEEE International Symposium on Circuits and Systems, 1437-1440, 2009 | 13 | 2009 |
| Non-volatile array wakeup and backup sequencing control SC Bartling, S Khanna US Patent 9,830,964, 2017 | 12 | 2017 |
| Error detection in nonvolatile logic arrays using parity SC Bartling, S Khanna US Patent 8,854,079, 2014 | 12 | 2014 |
| Spiroheterocycles. Part 23. Investigation on the Reactions of Indole‐2, 3‐diones with 2‐Aminothiophenol and 2‐Aminophenol. KC Joshi, A Dandia, S Khanna ChemInform 21 (50), no-no, 1990 | 12 | 1990 |
