| A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, 2015 | 90 | 2015 |
| A reference-less clock and data recovery circuit using phase-rotating phase-locked loop G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of Solid-State Circuits 49 (4), 1036-1047, 2014 | 64 | 2014 |
| A 12-Gb/s-16.8-dBm OMA sensitivity 23-mW optical receiver in 65-nm CMOS MG Ahmed, M Talegaonkar, A Elkholy, G Shu, A Elmallah, A Rylyakov, ... IEEE Journal of Solid-State Circuits 53 (2), 445-457, 2017 | 57 | 2017 |
| A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS J Zhu, RK Nandwana, G Shu, A Elkholy, SJ Kim, PK Hanumolu IEEE Journal of Solid-State Circuits 52 (1), 8-20, 2016 | 48 | 2016 |
| 15.4 A 20-to-1000MHz±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 47 | 2014 |
| 8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 47 | 2014 |
| Low-jitter multi-output all-digital clock generator using DTC-based open loop fractional dividers A Elkholy, S Saxena, G Shu, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (6), 1806-1817, 2018 | 40 | 2018 |
| 3.8 A 0.45-to-0.7 V 1-to-6Gb/S 0.29-to-0.58 pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS WS Choi, G Shu, M Talegaonkar, Y Liu, D Wei, L Benini, PK Hanumolu 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 39 | 2015 |
| A burst-mode digital receiver with programmable input jitter filtering for energy proportional links WS Choi, T Anand, G Shu, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (3), 737-748, 2015 | 33 | 2015 |
| Fractional-N PLL-based CDR with a low-frequency reference G Shu, MN Elzeftawi, AM Elkholy US Patent 9,306,730, 2016 | 23 | 2016 |
| A 2.8 mW/Gb/s, 14 Gb/s serial link transceiver S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2017 | 21 | 2017 |
| 23.1 a 16mb/s-to-8gb/s 14.1-to-5.9 pj/b source synchronous transceiver using dvfs and rapid on/off in 65nm cmos G Shu, WS Choi, S Saxena, SJ Kim, M Talegaonkar, R Nandwana, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2016 | 15 | 2016 |
| A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353, 2015 | 15 | 2015 |
| A 0.45–0.7 V 1–6 Gb/s 0.29–0.58 pJ/b source-synchronous transceiver using near-threshold operation WS Choi, G Shu, M Talegaonkar, Y Liu, D Wei, L Benini, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (3), 884-895, 2018 | 14 | 2018 |
| A 10-Gb/s/ch, 0.6-pJ/bit/mm power scalable rapid-ON/OFF transceiver for on-chip energy proportional interconnects D Wei, T Anand, G Shu, JE Schutt-Ainé, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (3), 873-883, 2017 | 13 | 2017 |
| A fast power-on 2.2 Gb/s burst-mode digital CDR with programmable input jitter filtering WS Choi, T Anand, G Shu, PK Hanumolu 2013 Symposium on VLSI Circuits, C280-C281, 2013 | 11 | 2013 |
| A 5Gb/s 2.6 mW/Gb/s reference-less half-rate PRPLL-based digital CDR G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... 2013 Symposium on VLSI Circuits, C278-C279, 2013 | 8 | 2013 |
| Injection-locking PLL with frequency drift tracking and duty-cycle distortion cancellation G Shu, FY Liu, S Yang, ZS Shehadeh, EY Chang US Patent 10,110,239, 2018 | 7 | 2018 |
| A 45–75MHz 197–452µW oscillator with 164.6dB FoM and 2.3psrmsperiod jitter in 65nm CMOS J Zhu, M Mahalley, G Shu, WS Choi, RK Nandwana, A Elkholy, B Sahoo, ... 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 7 | 2017 |
| A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter G Shu, Y Guo, J Ren, M Fan, F Ye Analog Integrated Circuits and Signal Processing 67, 95-102, 2011 | 6 | 2011 |
