Shirshendu Das
Shirshendu Das
Assistant Professor, Indian Institute of Technology Hyderabad, Telangana, India
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Cited by
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Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines
D Deb, J Jose, S Das, HK Kapoor
Journal of Parallel and Distributed Computing 123, 118-129, 2019
Victim retention for reducing cache misses in tiled chip multiprocessors
S Das, HK Kapoor
Microprocessors and Microsystems 38 (4), 263-275, 2014
Exploration of migration and replacement policies for dynamic NUCA over tiled CMPs
S Das, HK Kapoor
2015 28th International Conference on VLSI Design, 141-146, 2015
Static energy reduction by performance linked cache capacity management in tiled cmps
HK Kapoor, S Das, S Chakraborty
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 1913-1918, 2015
Dynamic associativity management using fellow sets
S Das, HK Kapoor
2013 International Symposium on Electronic System Design, 133-137, 2013
Towards a better cache utilization using controlled cache partitioning
PD Halwe, S Das, HK Kapoor
2013 IEEE 11th International Conference on Dependable, Autonomic and Secure …, 2013
A fairness conscious cache replacement policy for last level cache
KK Dutta, PN Tanksale, S Das
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 695-700, 2021
Random-LRU: a replacement policy for chip multiprocessors
S Das, N Polavarapu, PD Halwe, HK Kapoor
VLSI Design and Test: 17th International Symposium, VDAT 2013, Jaipur, India …, 2013
A survey on cache timing channel attacks for multicore processors
J Kaur, S Das
Journal of Hardware and Systems Security 5 (2), 169-189, 2021
Dynamic associativity management in tiled CMPs by runtime adaptation of fellow sets
S Das, HK Kapoor
IEEE Transactions on Parallel and Distributed Systems 28 (8), 2229-2243, 2017
A framework for block placement, migration, and fast searching in tiled-DNUCA architecture
S Das, HK Kapoor
ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (1 …, 2016
Towards a better cache utilization by selective data storage for CMP last level caches
S Das, HK Kapoor
2016 29th International Conference on VLSI Design and 2016 15th …, 2016
RT-DVS for power optimization in multiprocessor real-time systems
BV Naik, S Das, HK Kapoor
2014 International Conference on Information Technology, 24-29, 2014
Exploiting secrets by leveraging dynamic cache partitioning of last level cache
A Agarwal, J Kaur, S Das
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks
J Kaur, S Das
Journal of Systems Architecture 135, 102805, 2023
BHT-NoC: Blaming hardware trojans in NoC routers
B Bisht, S Das
Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors
HK Kapoor, P Kanakala, M Verma, S Das
The Journal of Supercomputing 65, 771-796, 2013
State preserving dynamic dram bank re-configurations for enhanced power efficiency
K Goswami, HK Mondal, S Das, DS Banerjee
20th International Symposium on Quality Electronic Design (ISQED), 131-137, 2019
Dynamic thermal management by using task migration in conjunction with frequency scaling for chip multiprocessors
AV Umdekar, A Nath, S Das, HK Kapoor
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
Latency aware block replacement for l1 caches in chip multiprocessor
S Das, HK Kapoor
2017 IEEE computer society annual symposium on VLSI (ISVLSI), 182-187, 2017
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