Devendra Sadana
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연도
Fin FET devices from bulk semiconductor and method for forming
DM Fried, EJ Nowak, BA Rainey, DK Sadana
US Patent 6,642,090, 2003
3582003
SOI CMOS structure
W Chen, DK Sadana, Y Taur
US Patent 5,767,549, 1998
3001998
Method of preventing surface roughening during hydrogen prebake of SiGe substrates
H Chen, DM Mocuta, RJ Murphy, SW Bedell, DK Sadana
US Patent 6,958,286, 2005
2762005
Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene
J Kim, C Bayram, H Park, CW Cheng, C Dimitrakopoulos, JA Ott, ...
Nature communications 5 (1), 1-7, 2014
2732014
Epitaxial lift-off process for gallium arsenide substrate reuse and flexible electronics
CW Cheng, KT Shiu, N Li, SJ Han, L Shi, DK Sadana
Nature communications 4 (1), 1-7, 2013
2362013
Spalling methods to form multi-junction photovoltaic structure
SW Bedell, DK Sadana, D Shahrjerdi
US Patent 8,927,318, 2015
2162015
Efficient and bright organic light-emitting diodes on single-layer graphene electrodes
N Li, S Oida, GS Tulevski, SJ Han, JB Hannon, DK Sadana, TC Chen
Nature communications 4 (1), 1-7, 2013
2082013
Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys
B Hekmatshoar-Tabari, M Hopstaken, DG Park, DK Sadana, GG Shahidi, ...
US Patent 8,778,448, 2014
1962014
Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys
B Hekmatshoar-Tabari, M Hopstaken, DG Park, DK Sadana, GG Shahidi, ...
US Patent 9,099,585, 2015
1952015
Heterojunction III-V photovoltaic cell fabrication
SW Bedell, NS Cortes, KE Fogel, D Sadana, G Shahidi, D Shahrjerdi
US Patent 8,802,477, 2014
1922014
Silicon-on-insulator vertical array device trench capacitor DRAM
CJ Radens, GB Bronner, TC Chen, B Davari, JA Mandelman, D Moy, ...
US Patent 6,566,177, 2003
1912003
Layer-resolved graphene transfer via engineered strain layers
J Kim, H Park, JB Hannon, SW Bedell, K Fogel, DK Sadana, ...
Science 342 (6160), 833-836, 2013
1872013
Patterned SOI regions in semiconductor chips
B Davari, DK Sadana, GG Shahidi, S Tiwari
US Patent 6,333,532, 2001
1842001
SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
BB Doris, D Chidambarrao, X Baie, JA Mandelman, DK Sadana, ...
US Patent 6,717,216, 2004
1672004
Kerf-less removal of Si, Ge, and III–V layers by controlled spalling to enable low-cost PV technologies
SW Bedell, D Shahrjerdi, B Hekmatshoar, K Fogel, PA Lauro, JA Ott, ...
IEEE Journal of Photovoltaics 2 (2), 141-147, 2012
1652012
Techniques for Layer Transfer Processing
S Bedell, K Fogel, B Furman, S Purushothaman, D Sadana, A Topol
US Patent App. 11/840,389, 2007
1652007
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, D Shahrjerdi, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
1592009
Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
E Leobandung, DK Sadana, DJ Schepis, GG Shahidi
US Patent 6,214,694, 2001
1542001
Interactions of thin Ti films with Si, SiO2, Si3N4, and SiOxNy under rapid thermal annealing
AE Morgan, EK Broadbent, KN Ritz, DK Sadana, BJ Burrow
Journal of applied physics 64 (1), 344-353, 1988
1511988
Mechanisms of amorphization and recrystallization in ion implanted III–V compound semiconductors
DK Sadana
Nuclear Instruments and Methods in Physics Research Section B: Beam …, 1985
1491985
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