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Sai Kiran Cherupally
Sai Kiran Cherupally
asu.edu의 이메일 확인됨
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ECG authentication hardware design with low-power signal processing and neural network optimization with low precision and structured compression
SK Cherupally, S Yin, D Kadetotad, G Srivastava, C Bae, SJ Kim, J Seo
IEEE transactions on biomedical circuits and systems 14 (2), 198-208, 2020
292020
A smart hardware security engine combining entropy sources of ECG, HRV, and SRAM PUF for authentication and secret key generation
SK Cherupally, S Yin, D Kadetotad, C Bae, SJ Kim, J Seo
IEEE Journal of Solid-State Circuits 55 (10), 2680-2690, 2020
192020
Modeling and optimization of SRAM-based in-memory computing hardware design
J Saikia, S Yin, SK Cherupally, B Zhang, J Meng, M Seok, JS Seo
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 942-947, 2021
142021
ECG authentication neural network hardware design with collective optimization of low precision and structured compression
SK Cherupally, G Srivastava, S Yin, D Kadetotad, C Bae, SJ Kim, J Seo
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
102019
Improving the accuracy and robustness of rram-based in-memory computing against rram hardware noise and adversarial attacks
SK Cherupally, J Meng, AS Rakin, S Yin, I Yeo, S Yu, D Fan, JS Seo
Semiconductor Science and Technology 37 (3), 034001, 2022
82022
A 1.23-ghz 16-kb programmable and generic processing-in-sram accelerator in 65nm
A Sridharan, S Angizi, SK Cherupally, F Zhang, JS Seo, D Fan
ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022
72022
Leveraging noise and aggressive quantization of in-memory computing for robust dnn hardware against adversarial input and weight attacks
SK Cherupally, AS Rakin, S Yin, M Seok, D Fan, J Seo
2021 58th ACM/IEEE Design Automation Conference (DAC), 559-564, 2021
72021
Improving DNN hardware accuracy by in-memory computing noise injection
SK Cherupally, J Meng, AS Rakin, S Yin, M Seok, D Fan, JS Seo
IEEE Design & Test 39 (4), 71-80, 2021
62021
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification
SK Venkataramanaiah, J Meng, HS Suh, I Yeo, J Saikia, SK Cherupally, ...
ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC), 89-92, 2022
32022
Hierarchical Random Boolean Network Reservoirs
SK Cherupally
32018
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity
SK Venkataramanaiah, J Meng, HS Suh, I Yeo, J Saikia, SK Cherupally, ...
IEEE Journal of Solid-State Circuits, 2023
22023
Smart hardware security engine using biometric features and hardware-specific features
J Seo, S Yin, SK Cherupally
US Patent 11,698,952, 2023
2023
Methods of training deep neural networks (dnn) using signal non-idealities and quantization associated with in-memory operations and related devices
AS Rakin, D Fan, SK Cherupally, J Seo
US Patent App. 17/931,682, 2023
2023
Hardware noise-aware training for improving accuracy of in-memory computing-based deep neural network hardware
SK Cherupally, J Meng, S Yin, D Fan
US Patent App. 17/714,677, 2022
2022
Machine Learning Assisted Security for Edge Computing Applications
SK Cherupally
Arizona State University, 2022
2022
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation
SK Cherupally, S Yin, D Kadetotad, C Bae, SJ Kim, JS Seo
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 145-148, 2019
2019
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