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Kean Hong Boey
Kean Hong Boey
Senior Design Engineer, Intel Corporation
Verified email at intel.com
Title
Cited by
Cited by
Year
Random clock against differential power analysis
KH Boey, Y Lu, M O'Neill, R Woods
2010 IEEE Asia Pacific Conference on Circuits and Systems, 756-759, 2010
282010
Security of AES Sbox designs to power analysis
KH Boey, P Hodgers, Y Lu, M O'Neill, R Woods
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
142010
Practical comparison of differential power analysis techniques on an ASIC implementation of the AES algorithm
Y Lu, KH Boey, M O'Neill, JV McCanny
IET Irish Signals and Systems Conference (ISSC 2009), 1-6, 2009
132009
How resistant are sboxes to power analysis attacks?
KH Boey, M O'Neill, R Woods
2011 4th IFIP International Conference on New Technologies, Mobility and …, 2011
72011
Lightweight DPA resistant solution on FPGA to counteract power models
Y Lu, KH Boey, P Hodgers, M O'Neill
2010 International Conference on Field-Programmable Technology, 178-183, 2010
72010
Differential power analysis of CAST-128
KH Boey, Y Lu, M O'Neill, R Woods
2010 IEEE Computer Society Annual Symposium on VLSI, 143-148, 2010
72010
Variable window power spectral density attack
P Hodgers, KH Boey, M O'Neill
2011 IEEE International Workshop on Information Forensics and Security, 1-6, 2011
62011
Thread efficiency for a multi-threaded network processor
LB Lim, KH Boey, KLK Puah
US Patent App. 10/262,031, 2004
62004
SEED masking implementations against power analysis attacks
Y Lu, KH Boey, P Hodgers, M O'Neill
2010 IEEE Asia Pacific Conference on Circuits and Systems, 1199-1202, 2010
52010
Is the differential frequency-based attack effective against random delay insertion?
Y Lu, KH Boey, M O'Neill, JV McCanny, A Satoh
2009 IEEE Workshop on Signal Processing Systems, 051-056, 2009
52009
Power spectral density side channel attack overlapping window method
P Hodgers, KH Boey, M O'Neill
2011 14th Euromicro Conference on Digital System Design, 274-278, 2011
32011
Serial interface logic built in self test methodology
KH Boey, KS Yap, WM Ng
2008 33rd IEEE/CPMT International Electronics Manufacturing Technology …, 2008
12008
Power Spectral Density Side Channel Attack Overlapping Window Method
M O'Neill, KH Boey, P Hodgers
2011
Differential Power Analysis Resistance of Camellia and Countermeasure Strategy
Y Lu, KH Boey, M O'Neill, J McCanny
IEEE International Conference on Field-Programmable Technology, 2009
2009
USB2. 0 Logic Built In Self Test Methodology
KH Boey, KS Yap, WM Ng
2008 17th Asian Test Symposium, 266-266, 2008
2008
Soft IP Integration and Reuse Challenges in Intel Entry Level Network Processor
WM Ng, KS Yap, KH Boey
2006 IEEE International Conference on Semiconductor Electronics, 414-417, 2006
2006
Clock gating methodology for high performance network processor in 90nm
KS Yap, KH Boey
2004 IEEE International Conference on Semiconductor Electronics, 5 pp., 2004
2004
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