Israel Koren
Israel Koren
Professor of Computer Engineering, University of Massachusetts
Verified email at ecs.umass.edu - Homepage
Title
Cited by
Cited by
Year
Computer arithmetic algorithms
I Koren
A.K. Peters, Ltd, 2002
1824*2002
Fault-tolerant systems
I Koren, CM Krishna
Morgan Kaufmann, 2020
11712020
Fault injection attacks on cryptographic devices: Theory, practice, and countermeasures
A Barenghi, L Breveglieri, I Koren, D Naccache
Proceedings of the IEEE 100 (11), 3056-3076, 2012
4872012
Error analysis and detection procedures for a hardware implementation of the advanced encryption standard
G Bertoni, L Breveglieri, I Koren, P Maistri, V Piuri
IEEE transactions on Computers 52 (4), 492-505, 2003
4152003
Defect tolerance in VLSI circuits: techniques and yield analysis
I Koren, Z Koren
Proceedings of the IEEE 86 (9), 1819-1838, 1998
2911998
System-level power-aware design techniques in real-time systems
OS Unsal, I Koren
Proceedings of the IEEE 91 (7), 1055-1069, 2003
2382003
Methods and apparatus for detecting defects in imaging arrays by image analysis
GH Chapman, I Koren, Z Koren, J Dudas, C Jung
US Patent 8,009,209, 2011
2202011
Complete and partial fault tolerance of feedforward neural nets
DS Phatak, I Koren
IEEE Transactions on Neural Networks 6 (2), 446-456, 1995
2011995
A reconfigurable and fault-tolerant VLSI multiprocessor array
I Koren
Proceedings of the 8th annual symposium on Computer Architecture, 425-442, 1981
1701981
Fault tolerance in VLSI circuits
I Koren, AD Singh
Computer 23 (7), 73-83, 1990
1361990
Temperature aware floorplanning
Y Han, I Koren, CA Moritz
Workshop on Temperature Aware Computer Systems 24, 2005
1132005
Optimal aspect ratios of building blocks in VLSI
S Wimer, I Koren, I Cederbaum
IEEE transactions on computer-aided design of integrated circuits and …, 1989
1111989
Yield models for defect-tolerant VLSI circuits: A review
I Koren, CH Stapper
Defect and Fault Tolerance in VLSI Systems, 1-21, 1989
1111989
Connectivity and performance tradeoffs in the cascade correlation learning architecture
DS Phatak, I Koren
IEEE Transactions on Neural Networks 5 (6), 930-935, 1994
1091994
A unified negative-binomial distribution for yield analysis of defect-tolerant circuits
I Koren, Z Koren, CH Stepper
IEEE Transactions on Computers 42 (6), 724-734, 1993
1061993
Floorplans, planar graphs, and layouts
S Wimer, I Koren, I Cederbaum
IEEE Transactions on Circuits and Systems 35 (3), 267-278, 1988
1061988
Evaluating elementary functions in a numerical coprocessor based on rational approximations
I Koren, O Zinaty
IEEE Transactions on Computers 39 (8), 1030-1037, 1990
1041990
On area and yield considerations for fault-tolerant VLSI processor arrays
I Koren, MA Breuer
IEEE Transactions on computers 100 (1), 21-27, 1984
1031984
Layout-synthesis techniques for yield enhancement
VKR Chiluvuri, I Koren
IEEE Transactions on Semiconductor Manufacturing 8 (2), 178-187, 1995
1011995
A data-driven VLSI array for arbitrary algorithms
I Koren, B Mendelson, I Peled, GM Silberman
Computer 21 (10), 30-43, 1988
1001988
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