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Kaushik Vaidyanathan
Kaushik Vaidyanathan
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Building trusted ICs using split fabrication
K Vaidyanathan, BP Das, E Sumbul, R Liu, L Pileggi
2014 IEEE international symposium on hardware-oriented security and trust …, 2014
1172014
Efficient and secure intellectual property (IP) design with split fabrication
K Vaidyanathan, R Liu, E Sumbul, Q Zhu, F Franchetti, L Pileggi
2014 IEEE international symposium on hardware-oriented security and trust …, 2014
822014
Detecting reliability attacks during split fabrication using test-only BEOL stack
K Vaidyanathan, BP Das, L Pileggi
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
462014
Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node
K Vaidyanathan, SH Ng, D Morris, N Lafferty, L Liebmann, M Bender, ...
Design for Manufacturability through Design-Process Integration VI 8327, 164-175, 2012
372012
Design automation framework for application-specific logic-in-memory blocks
Q Zhu, K Vaidyanathan, O Shacham, M Horowitz, L Pileggi, F Franchetti
2012 IEEE 23rd International Conference on Application-Specific Systems …, 2012
322012
Design of embedded memory and logic based on pattern constructs
D Morris, K Vaidyanathan, N Lafferty, K Lai, L Liebmann, L Pileggi
2011 Symposium on VLSI Technology-Digest of Technical Papers, 104-105, 2011
262011
Enabling application-specific integrated circuits on limited pattern constructs
D Morris, V Rovner, L Pileggi, A Strojwas, K Vaidyanathan
2010 Symposium on VLSI Technology, 139-140, 2010
252010
Rethinking ASIC design with next generation lithography and process integration
K Vaidyanathan, R Liu, L Liebmann, K Lai, A Strojwas, L Pileggi
Design for Manufacturability through Design-Process Integration VII 8684, 74-88, 2013
192013
Design implications of extremely restricted patterning
K Vaidyanathan, R Liu, L Liebmann, K Lai, AJ Strojwas, L Pileggi
Journal of Micro/Nanolithography, MEMS, and MOEMS 13 (3), 031309-031309, 2014
182014
Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling
LW Liebmann, K Vaidyanathan, LT Pileggi
SPIE PRESS, 2016
162016
Sub-20 nm design technology co-optimization for standard cell logic
K Vaidyanathan, L Liebmann, A Strojwas, L Pileggi
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 124-131, 2014
162014
Asymmetrical write driver for resistive memory
H Liu, DH Morris, S Manipatruni, K Vaidyanathan, IA Young, T Karnik
US Patent App. 15/164,665, 2017
152017
Synchronous circuit design with beyond-CMOS magnetoelectric spin–orbit devices toward 100-mV logic
H Liu, S Manipatruni, DH Morris, K Vaidyanathan, DE Nikonov, T Karnik, ...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5 …, 2019
132019
Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip
K Vaidyanathan, Q Zhu, L Liebmann, K Lai, S Wu, R Liu, Y Liu, A Strojwas, ...
Journal of Micro/Nanolithography, MEMS, and MOEMS 14 (1), 011007-011007, 2015
132015
Enabling high-performance heterogeneous TFET/CMOS logic with novel circuits using TFET unidirectionality and low-VDD operation
DH Morris, K Vaidyanathan, UE Avci, H Liu, T Karnik, IA Young
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
122016
Nonvolatile sram
H Liu, S Manipatruni, DH Morris, K Vaidyanathan, N Mukherjee, ...
US Patent 10,748,602, 2020
102020
Overcoming interconnect scaling challenges using novel process and design solutions to improve both high-speed and low-power computing modes
K Vaidyanathan, DH Morris, UE Avci, IS Bhati, L Subramanian, J Gaur, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.1. 1-20.1. 4, 2017
92017
Local loops for robust inter-layer routing at sub-20 nm nodes
W Huang, D Morris, N Lafferty, L Liebmann, K Vaidyanathan, K Lai, ...
Design for Manufacturability through Design-Process Integration VI 8327, 111-119, 2012
82012
Exploiting challenges of sub-20 nm CMOS for affordable technology scaling
K Vaidyanathan
arXiv preprint arXiv:1509.00885, 2015
72015
HotGauge: a methodology for characterizing advanced hotspots in modern and next generation processors
A Hankin, D Werner, M Amiraski, J Sebot, K Vaidyanathan, M Hempstead
2021 IEEE International Symposium on Workload Characterization (IISWC), 163-175, 2021
52021
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