| A High-Speed Low-Complexity Modified FFT Processor for High Rate WPAN Applications T Cho, H Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (1), 187-191, 2012 | 92 | 2012 |
| A high-speed low-complexity modified radix-2 5 FFT processor for gigabit WPAN applications T Cho, H Lee, J Park, C Park 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 1259-1262, 2011 | 52 | 2011 |
| FPGA Implementation and Performance Evaluation of FFT Core Hardware Architecture for Channelizer of Electronic Warfare Digital Receiver T Cho, Y Seo, H Na, T Kim, S Park 2017 대한전자공학회 추계학술대회 (2017 IEIE Fall Conference), 428-430, 2017 | | 2017 |
| Implementation and Performance Evaluation of High Level FFT Simulator for Channelizer of Broadband Digital Receiver on FPGA Platform H Na, T Cho, J Song, H Ju, J Kang 2017 대한전자공학회 추계학술대회 (2017 IEIE Fall Conference), 425-427, 2017 | | 2017 |
| High-Speed Low-Complexity MDF Hardware Architecture for Mixed-Radix FFT Computation T Thi Bao Nguyen, T Cho, H Lee 2015 대한전자공학회 추계학술대회 (2015 IEIE Fall Conference), 158-160, 2015 | | 2015 |
| High-Speed Low-Complexity Radix-2 to the Fifth Fast Fourier Transform Apparatus and Method H Lee, T Cho KR Patent 10-1,334,494, 2013 | | 2013 |
| Bio-inspired fault tolerant wireless communication system KY Wang, BS Kim, T Cho, DJ Chung, J Chung 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 254-258, 2012 | | 2012 |
