| Architecture, chip, and package co-design flow for 2.5 D IC design enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, V Chaitanya, K Chekuri, N Dasari, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 49 | 2019 |
| Architecture, chip, and package codesign flow for interposer-based 2.5-D chiplet integration enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, VCK Chekuri, NM Rahman, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (11 …, 2020 | 47 | 2020 |
| Heterogeneous mixed-signal monolithic 3-D in-memory computing using resistive RAM G Murali, X Sun, S Yu, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (2), 386-396, 2020 | 34 | 2020 |
| RTL-to-GDS design tools for monolithic 3D ICs J Kim, G Murali, P Vanna-Iampikul, E Lee, D Kim, A Chaudhuri, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 8 | 2020 |
| Advances in design and test of monolithic 3-D ICs A Chaudhuri, S Banerjee, H Park, J Kim, G Murali, E Lee, D Kim, SK Lim, ... IEEE Design & Test 37 (4), 92-100, 2020 | 8 | 2020 |
| Breaking barriers: Maximizing array utilization for compute in-memory fabrics B Crafton, S Spetalnick, G Murali, T Krishna, SK Lim, A Raychowdhury 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration …, 2020 | 6 | 2020 |
| ART-3D: Analytical 3D placement with reinforced parameter tuning for monolithic 3D ICs G Murali, SM Shaji, A Agnesina, G Luo, SK Lim Proceedings of the 2022 International Symposium on Physical Design, 97-104, 2022 | 5 | 2022 |
| A machine learning-powered tier partitioning methodology for monolithic 3-D ICs YC Lu, S Pentapati, L Zhu, G Murali, K Samadi, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 5 | 2021 |
| Design automation and test solutions for monolithic 3D ICs L Zhu, A Chaudhuri, S Banerjee, G Murali, P Vanna-Iampikul, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-49, 2021 | 4 | 2021 |
| Heterogeneous 3d ics: Current status and future directions for physical design technologies G Murali, SK Lim 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 146-151, 2021 | 3 | 2021 |
| On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs G Murali, A Iyer, L Zhu, J Tong, FM Martínez, SR Srinivasa, T Karnik, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 1 | 2023 |
| 3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators G Murali, A Iyer, N Ravichandran, SK Lim 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | | 2023 |
| A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers G Murali, A Agnesina, SK Lim ACM Transactions on Design Automation of Electronic Systems 28 (5), 1-22, 2023 | | 2023 |
| ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs S Banerjee, A Chaudhuri, J Kim, G Murali, M Nelson, SK Lim, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | | 2021 |
| Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems G Murali, H Park, E Qin, HM Torun, MA Dolatsara, M Swaminathan, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 605-616, 2021 | | 2021 |
| Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics B Crafton, S Spetalnick, G Murali, T Krishna, SK Lim, A Raychowdhury VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on …, 2021 | | 2021 |
| Clock Network Design for 2.5 D Heterogeneous Systems G Murali Georgia Institute of Technology, 2020 | | 2020 |
Sung Kyu LimProfessor, Georgia Institute of TechnologyVerified email at ece.gatech.edu
