| 300mm heterogeneous 3D integration of record performance layer transfer germanium PMOS with silicon NMOS for low power high performance logic applications W Rachmady, A Agrawal, SH Sung, G Dewey, S Chouksey, B Chu-Kung, ... 2019 IEEE International Electron Devices Meeting (IEDM), 29.7. 1-29.7. 4, 2019 | 180 | 2019 |
| Re-growing source/drain regions from un-relaxed silicon layer CH Wann, CH Ko, YT Huang, CY Huang US Patent 8,609,518, 2013 | 180 | 2013 |
| 3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact … HW Then, S Dasgupta, M Radosavljevic, P Agababov, I Ban, R Bristol, ... 2019 IEEE International Electron Devices Meeting (IEDM), 17.3. 1-17.3. 4, 2019 | 176 | 2019 |
| Nitrogen-passivated dielectric/InGaAs interfaces with sub-nm equivalent oxide thickness and low interface trap densities V Chobpattana, J Son, JJM Law, R Engel-Herbert, CY Huang, S Stemmer Applied Physics Letters 102 (2), 2013 | 106 | 2013 |
| 3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling CY Huang, G Dewey, E Mannebach, A Phan, P Morrow, W Rachmady, ... 2020 IEEE International Electron Devices Meeting (IEDM), 20.6. 1-20.6. 4, 2020 | 71 | 2020 |
| Record Ion(0.50 mA/µm at VDD= 0.5 V and Ioff= 100 nA/µm) 25 nm-gate-length ZrO2/InAs/InAlAs MOSFETs S Lee, V Chobpattana, CY Huang, BJ Thibeault, W Mitchell, S Stemmer, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 60 | 2014 |
| High performance raised source/drain InAs/In0. 53Ga0. 47As channel metal-oxide-semiconductor field-effect-transistors with reduced leakage using a vertical spacer S Lee, CY Huang, D Cohen-Elias, JJM Law, V Chobpattanna, S Krämer, ... Applied Physics Letters 103 (23), 2013 | 57 | 2013 |
| Highly scalable raised source/drain InAs quantum well MOSFETs exhibiting ION= 482 μA/μm at IOFF= 100 nA/μm and VDD= 0.5 V S Lee, CY Huang, D Cohen-Elias, BJ Thibeault, W Mitchell, ... IEEE Electron Device Lett 35 (6), 621-623, 2014 | 42 | 2014 |
| Low Power III–V InGaAs MOSFETs featuring InP recessed source/drain spacers with Ion=120 µA/µm at Ioff=1 nA/µm and VDS=0.5 V CY Huang, S Lee, V Chobpattana, S Stemmer, AC Gossard, B Thibeault, ... 2014 IEEE International Electron Devices Meeting, 25.4. 1-25.4. 4, 2014 | 28 | 2014 |
| Record extrinsic transconductance (2.45 mS/µm at VDS= 0.5 V) InAs/In0.53Ga0.47As channel MOSFETs using MOCVD source-drain regrowth S Lee, CY Huang, AD Carter, DC Elias, JJM Law, V Chobpattana, ... 2013 Symposium on VLSI Technology, T246-T247, 2013 | 26 | 2013 |
| Ultrathin InAs-channel MOSFETs on Si substrates CY Huang, X Bao, Z Ye, S Lee, H Chiang, H Li, V Chobpattana, ... 2015 International Symposium on VLSI Technology, Systems and Applications, 1-2, 2015 | 14 | 2015 |
| 12 nm-gate-length ultrathin-body InGaAs/InAs MOSFETs with 8.3•105ION/IOFF CY Huang, P Choudhary, S Lee, S Kraemer, V Chobpattana, B Thibeault, ... 2015 73rd Annual Device Research Conference (DRC), 260-260, 2015 | 13 | 2015 |
| Record-performance In (Ga) As MOSFETS targeting ITRS high-performance and low-power logic MJ Rodwell, CY Huang, S Lee, V Chobpattana, B Thibeault, W Mitchell, ... ECS Transactions 66 (4), 135, 2015 | 13 | 2015 |
| Nanometer InP electron devices for VLSI and THz applications MJW Rodwell, S Lee, CY Huang, D Elias, V Chobpattanna, J Rode, ... 72nd Device Research Conference, 215-216, 2014 | 13 | 2014 |
| Co-doping of InxGa1− xAs with silicon and tellurium for improved ultra-low contact resistance JJM Law, AD Carter, S Lee, CY Huang, H Lu, MJW Rodwell, AC Gossard Journal of crystal growth 378, 92-95, 2013 | 13 | 2013 |
| High transconductance surface channel In0.53Ga0.47As MOSFETs using MBE source-drain regrowth and surface digital etching S Lee, CY Huang, AD Carter, JJM Law, DC Elias, V Chobpattana, ... 2013 International Conference on Indium Phosphide and Related Materials …, 2013 | 13 | 2013 |
| Reduction of leakage current in In0. 53Ga0. 47As channel metal-oxide-semiconductor field-effect-transistors using AlAs0. 56Sb0. 44 confinement layers CY Huang, S Lee, D Cohen-Elias, JJM Law, AD Carter, V Chobpattana, ... Applied Physics Letters 103 (20), 2013 | 11 | 2013 |
| Opportunities in 3-D stacked CMOS transistors M Radosavljević, CY Huang, W Rachmady, SH Seung, NK Thomas, ... 2021 IEEE International Electron Devices Meeting (IEDM), 34.1. 1-34.1. 4, 2021 | 9 | 2021 |
| Formation of sub-10 nm width InGaAs finFETs of 200 nm height by atomic layer epitaxy D Cohen-Elias, JJM Law, HW Chiang, A Sivananthan, C Zhang, ... 71st Device Research Conference, 1-2, 2013 | 8 | 2013 |
| III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications CY Huang University of California, Santa Barbara, 2015 | 7 | 2015 |
